VIS
Description
VG3617161DT
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
The VG3617161DT is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V
power supply. This SDRAM is delicately designed with performance concern for current high-speed applica-
tion. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It
is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features
•
Single 3.3V +/- 0.3V power supply
•
Clock Frequency: 250MHz, 200MHz, 183MHz, 166MHz, 143MHz, 125MHz
•
Fully synchronous with all signals referenced to a positive clock edge
•
Programmable CAS Iatency (2,3)
•
Programmable burst length (1,2,4,8,& Full page)
•
Programmable wrap sequence (Sequential/Interleave)
•
Automatic precharge and controlled precharge
•
Auto refresh and self refresh modes
•
Dual internal banks controlled by A11(Bank select)
•
Simultaneous and independent two bank operation
•
I/O level : LVTTL interface
•
Random column access in every cycle
•
X16 organization
•
Byte control by LDQM and UDQM
•
4096 refresh cycles/64ms
•
Burst termination by burst stop and precharge command
Document:1G5-0167
Rev.5
Page 1
VIS
Pin Configuration
VG3617161DT
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
50-Pin Plastic TSOP(II)(400 mil)
V
DD
DQ0
DQ1
1
2
3
4
5
6
7
50
49
48
47
46
45
44
V
SS
DQ15
DQ14
V
SSQ
DQ2
DQ3
V
SSQ
DQ13
DQ12
V
DDQ
DQ4
DQ5
V
DDQ
DQ11
DQ10
VG3617161DT
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SSQ
DQ6
DQ7
V
SSQ
DQ9
DQ8
V
DDQ
LDQM
WE
CAS
RAS
CS
(BS)A
11
A
10
A
0
A
1
A
2
A
3
V
DD
V
DDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
(VG3617161DT)
Pin Name
A0-A11
Function
Address inputs
- Row address
A0-A10
- Column address A0-A7
A11: Bank select
Data-in/data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Pin Name
LDQM,
UDQM
Function
Lower DQ mask enable and
Upper DQ mark enable
DQ0~DQ15
RAS
CAS
WE
V
SS
V
DD
CLK
CKE
CS
V
DDQ
V
SSQ
Clock input
Clock enable
Chip select
Supply voltage for DQ
Ground for DQ
Document:1G5-0167
Rev.5
Page 2
VIS
Absolute Maximum Ratings
VG3617161DT
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
Parameter
Voltage on any pin relative to Vss
Supply voltage relative to Vss
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
V
IN
,V
OUT
V
DD
,V
DDQ
I
OUT
P
D
T
OPT
T
STG
Value
-1.0 to +4.6
-1.0 to +4.6
50
1.0
0 to + 70
-55 to + 125
Unit
V
V
mA
W
℃
℃
Recommended DC Operating Conditions
Parameter
Supply Voltage
Input High Voltage, all inputs
Input Low Voltage, all inputs
Symbol
V
DD
V
IH
V
IL
Min
3.0
2.0
-0.3
Typ
3.3
－
－
Max
3.6
V
DD
+0.3
0.8
Unit
V
V
V
Note
1
2
Note 1.Overshoot limit : V
IH(MAX.)
=V
DDQ
+2.0V with a pulse width < 3ns
2.Undershoot limit : V
IL
=V
SSQ
-2.0V with a pulse < 3ns and -1.5V with a pulse < 5ns
Parameter
I
IL
I
OL
( 0V
V
V
Description
Input Leakage Current
All other pins not under test = OV)
Min.
-5
Max.
5
Unit
A
A
Note
IN
DD
Output Leakage Current
Output disable, ( 0V
V
V
)
OUT
DDQ
LVTTL Output
”H”
Level Voltage
(l
OUT
= -2mA)
LVTTL Output
”L”
Level Voltage
(l
OUT
= 2mA)
-5
5
V
OH
V
OL
2.4
-
-
0.4
V
V
Document:1G5-0167
Rev.5
Page 3
VIS
Capacitance
(Ta=25°C,f=1MHZ)
VG3617161DT
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
Parameter
Input capacitance(CLK)
Input capacitance(all input pins except data
pins)
Data input/output capacitance
Symbol
C
11
C
12
C
I/O
Typ
2.5
2.5
4.0
Max
4
5
6.5
Unit
pF
pF
pF
Recommended D.C. Operating Conditions (V
DD
= 3.3V
Description/test condition
Operating Current
t
t
, Outputs Open
RC RC
min
Address changed once during t
CK(min)
.
Burst Length = 1 (One Bank Active)
Precharge Standby Current in non power-down mode
t
CK
= t
CK(min)
,
CS
V
IH
(min)
, CKE
V
IH
(min)
Input signals are changed once during 30ns.
Precharge Standby Current in non power-down mode
t
CK
=
, CKE
V
IH
(min)
,
0.3V, Ta = 0 ~ 70°C)
-4
-5
195
-5.5
190
-6
185
-7
175
-8
165
Unit Note
3,4
Min Max Min Max Min Max Min Max Min Max Min Max
Symbol
I
DD1
205
I
DD2N
90
90
90
90
90
90
3
CLK
V
IL
(max)
I
DD2NS
35
35
35
35
35
35
mA
Input signals are stable
Precharge Standby Current in power-down mode
t
CK
= t
CK
(min), CKE
V
IL
(max)
Precharge Standby Current in power-down mode
t
CK
=
, CKE
V
IL
(max)
, CLK
I
DD2P
3
3
3
3
3
3
3
V
IL
(max)
I
DD2PS
2.8
2.8
2.8
2.8
2.8
2.8
Active Standby Current in non power down mode
CKE
V
IH
(min)
, t
CK
= t
CK(min)
(Both Bank Actioe)
Active Standby Current in power-down
CKE
V
IL
(max)
, t
CK =
t
CK(min)
, CS
V
IH(min)
(Both
Bank Active)
Operating Current (Page Burst, and All Bank activated)
t
CCD
= t
CCD(min)
, Outputs Open, Multi-bank interleave,
gapless data
Refresh Current
t
RC
t
RC
(min)
(t
REF
= 64ms)
Self Refresh Current
CKE
0.2V
I
DD3N
I
DD3P
70
5
70
5
70
5
70
5
70
5
70
5
3
I
DD4
255
240
235
225
210
195
4,5
I
DD5
I
DD6
180
3.5
175
3.5
170
3.5
160
3.5
150
3.5
140
3.5
3
Document:1G5-0167
Rev.5
Page 4
VIS
A.C Characteristics: ( Note: 6, 7, 8, 9, 10)
Test Conditions:
(Ta=0 to 70°C V
DD
=3.3V
0.3V ,V
SS
=0V)
symbol
A.C. Parameter
Min
t
CH
t
CL
t
T
t
CK3
t
CK2
t
IS
t
IH
t
DS
t
DH
t
LZ
t
HZ3
t
HZ2
t
AC3
t
AC2
t
OH
t
RCD
t
RRD
t
CCD
t
DPL
t
RAS
t
RP
Clock high time
Clock low time
Transition time (Rise and
Fall)
Clock cycle time
CL* = 3
CL* = 2
Address/Control Input setup
time
Address/Control Input hold
time
Data Input setup time
Data Input hold time
Data output low impedance
Data output high
impedance
Access time from
CLK
(positive edge)
CL* = 3
CL* = 2
CL* = 3
CL* = 2
2
12
8
1
2tCK
24 100,000
15
1.8
1.8
0.5
4
-----
1.5
1
1.5
1
1
3.5
---
3.5
---
2
15
10
1
1tCK
+2ns
30
15
100,000
10
-4
Max
Min
2.3
2.3
0.5
5
-----
1.5
1
1.5
1
1
4.8
---
4.8
---
2
16.5
11
1
1tCK
+2ns
33
16.5
100,000
10
-5
Max
Min
2.3
2.3
0.5
5.5
-----
1.5
1
1.5
1
1
5
---
5
---
10
-5.5
Max
VG3617161DT
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
-6
Min
2.5
2.5
0.5
6
-----
2
1
2
1
1
5
---
5.5
---
2.3
18
12
1
1tCK
+1ns
36
18
100,000
2.5
20
14
1
1
42
20
10
Max
Min
2.5
2.5
0.5
7
10
2
1
2
1
1
-7
Max
Min
3
3
10
0.5
8
12
2
1
2
1
1
5
7
6
7
2.5
20
16
1
1
100,000
48
20
-8
Max
unit note
ns
10
6
7
6
7
9
Data output hold time
RAS to CAS delay
Row activate to row activate
delay
CAS to CAS Delay time
Last data in to precharge
Row activate to precharge
time
Precharge to refresh/row
activate
command
Data-in to ACT (REF) Com-
mand (CL = 3)
Data-in to ACT (REF) Com-
mand (CL = 2)
Row cycle time
(Special) Mode Register Set
Cycle time
Refresh time
Minimum CKE
”High”for
Self-
Refresh exit
Last data in to burst STOP
command
CLK
CLK
100,000
ns
ns
t
DAL3
t
DAL2
t
RC
t
RSC
t
REF
t
SRX
t
BDL
t
PDE
tDPL
+ t
RP
tDPL
+ t
RP
39
2
64
1
1
tDPL+
t
RP
tDPL
+t
RP
45
2
64
1
1
5
tDPL+
t
RP
tDPL
+t
RP
49.5
2
64
1
1
5
tDPL+
t
RP
tDPL+
t
RP
54
2
64
1
1
5
tDPL
+t
RP
tDPL
+t
RP
63
2
64
1
1
5
tDPL
+t
RP
tDPL
+t
RP
72
2
64
1
1
6
ns
CLK
ms
CLK
CLK
ns
Power Down Exit set-up time 3.5
Document:1G5-0167
Rev.5
Page 5
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