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IDT70V5378S100BC

Description
Four-Port SRAM, 32KX18, 3.6ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, BGA-256
Categorystorage    storage   
File Size390KB,29 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70V5378S100BC Overview

Four-Port SRAM, 32KX18, 3.6ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, BGA-256

IDT70V5378S100BC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeBGA
package instruction17 X 17 MM, 1 MM PITCH, BGA-256
Contacts256
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.B
Maximum access time3.6 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B256
JESD-609 codee0
length17 mm
memory density589824 bit
Memory IC TypeFOUR-PORT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of ports4
Number of terminals256
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Encapsulate equivalent codeBGA256,16X16,40
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.5 mm
Maximum standby current0.015 A
Minimum standby current3.15 V
Maximum slew rate0.24 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
width17 mm
Base Number Matches1
3.3V 64/32K X 18
SYNCHRONOUS
FOURPORT™ STATIC RAM
Features
IDT70V5388/78
True four-ported memory cells which allow simultaneous
access of the same memory location
Synchronous Pipelined device
– 64/32K x 18 organization
Pipelined output mode allows fast 200MHz operation
High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x
4 ports)
LVTTL I/O interface
High-speed clock to data access 3.0ns (max.)
3.3V Low operating power
Interrupt flags for message passing
Width and depth expansion capabilities
Counter wrap-around control
– Internal mask register controls counter wrap-around
– Counter-Interrupt flags to indicate wrap-around
Counter readback on address lines
Mask register readback on address lines
Global Master reset for all ports
Dual Chip Enables on all ports for easy depth expansion
Separate upper-word and lower-word controls on all ports
272-BGA package (27mm x 27mm 1.27mm ball pitch) and
256-BGA package (17mm x 17mm 1.0mm ball pitch)
Commercial and Industrial temperature ranges
JTAG boundary scan
MBIST (Memory Built-In Self Test) controller
Port - 1 Logic Block Diagram
(2)
R/
W
P1
UB
P1
CE
0P1
CE
1P1
LB
P1
OE
P1
0
1
1 /0
I/O
9P1
- I/O
17P1
I/O
0P1
- I/O
8P1
Port 1
I/O
Control
TRST
TMS
TCK
TDI
CLKMBIST
JTAG
Controller
MBIST
TDO
Addr.
Read
Back
Port 1
Readback
Register
MRST
A
0P1
- A
15P1
(1)
CNTRD
P1
MKRD
P1
MKLD
P1
CNTINC
P1
CNTLD
P1
CNTRST
P1
CLK
P1
MRST
CNTINT
P1
Port 1
Mask
Register
Priority
Decision
Logic
Port 1
Counter/
Address
Register
Port 1
Address
Decode
64KX18
Memory
Array
,
R/
W
P1
CE
0P1
CE
1P1
CLK
P1
Port 1
Interrupt
Logic
INT
P1
MRST
NOTE:
1. A
15
x is a NC for IDT70V5378.
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
5649 drw 01
AUGUST 2003
DSC-5649/3
1
©2003 Integrated Device Technology, Inc.
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