TLE 7209R
Overview
7 A H-Bridge for DC-Motor Applications
1.2
TLE 7209R
Pin Configuration
Preliminary Datasheet
1
1.1
• Operating supply voltage 5 V to 28 V
• Typical
R
DSon
= 150 mΩ for each output transistor
(at 25
°C)
Continuos DC load current 3.5 A (
T
C
< 100
°C)
Output current limitation at typ. 6.6 A
±
1.1 A
Short circuit shut down for output currents over 8 A
Logic- inputs TTL/CMOS-compatible
Operating-frequency up to 30 kHz
Over temperature protection
Short circuit protection
Undervoltage disable function
Diagnostic by SPI or Status-Flag (configurable)
Enable and Disable input
P-DSO-20-12 power package
P-DSO-20-10, -12, -16
Overview
Features
GND
SCK/SF
IN1
V
S
CP
V
S
OUT1
OUT1
SDO
SDI
GND
•
•
•
•
•
•
•
•
•
•
•
Type
TLE 7209R
Functional Description
on request
Ordering Code
Package
P-DSO-20-12
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
IN2
DIS
CSN
V
S
OUT2
OUT2
EN
DMS
GND
Metal slug is
connected to GND
pins internally
Figure 1
Pinout TLE 7209R
The TLE 7209R is an intelligent full H-Bridge, designed for the control of DC and stepper
motors in safety critical applications and under extreme environmental conditions.
The H-Bridge is protected against over temperature and short circuits and has an under
voltage lockout for all the supply voltages “
V
S
” (main DC power supply). All malfunctions
cause the output stages to go tristate.
The device is configurable by the DMS pin. When grounded, the device gives diagnostic
information via a simple error flag. When supplied with
V
CC
= 5 V, the device works in
SPI mode. In this mode, detailed failure diagnosis is available via the serial interface.
Preliminary Datasheet
1
V1.1, 2002-11-26
Preliminary Datasheet
2
V1.1, 2002-11-26
TLE 7209R
Overview
Pin Definitions and Functions
Pin. No.
1
2
3
4
Supply voltage for internal charge pump
Supply voltage
Output 1
Output 1
Serial data out
Serial data in
Ground
Ground
Diagnostic-Mode selection
(+ Supply voltage for SPI-Interface)
Enable
Output 2
Output 2
Supply voltage, must be connected to pin 5
Chip Select (low active)
Disable
Input 2
Ground
IN1
IN2
Direct
Input
Under
Voltage
EN
DIS
CSN
SDI
SDO
SCK/SF
SPI
8 Bit
Logic
and
Latch
Bias
TLE 7209R
Overview
1.3
Block Diagram
Symbol
GND
SCK/SF
IN1
Input 1
SPI-Clock/Status-flag
Ground
Function
DMS
V
S
CP
V
S
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Table 1
Pinning
GND
IN2
DIS
CSN
OUT2
OUT2
EN
DMS
GND
GND
SDI
SDO
OUT1
OUT1
V
S
CP
V
S
Charge
Pump
Fault-
Detect
Driver
OUT 1
&
Gate-
Control
OUT 2
V
S
Over
Temperature
GND
Figure 2
Block Diagram TLE 7209R
Preliminary Datasheet
3
V1.1, 2002-11-26
Preliminary Datasheet
4
V1.1, 2002-11-26
TLE 7209R
Circuit Description
TLE 7209R
Circuit Description
2
2.2
2.1
The bridge is controlled by the Inputs IN1, IN2, DIS and EN as shown in
Table 2.
The
outputs OUT1 and OUT2 are set to High or Low by the parallel inputs IN1 and IN2,
respectively. In addition, the outputs can be disabled (set to tristate) by the Disable and
Enable inputs DIS and EN.
Inputs IN1, IN2 and DIS have an internal pull-up. Input EN has an internal pull-down.
Functional Truth Table
Pos.
1. Forward
2. Reverse
3. Free-wheeling low
4. Free-wheeling high
5. Disable
6. Enable
7. IN1 disconnected
8. IN2 disconnected
9. DIS disconnected
10. EN disconnected
11. Current limit. active
12. Under Voltage
13. Over temperature
14. Over current
1)
2)
Circuit Description
Control Inputs
Power Stages
Four n-channel power-DMOS transistors build up the output H-bridge. Integrated circuits
protect the outputs against over current and over temperature if there is a short-circuit to
ground, to the supply voltage or across the load. Positive and negative voltage spikes,
which occur when switching inductive loads, are limited by integrated freewheeling
diodes. To drive the gates of the high-side DMOS, an internal charge pump is integrated
to generate a voltage higher than the supply voltage.
2.2.1
Chopper Current Limitation
DIS EN
L
L
L
L
H
X
L
L
Z
X
L
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
Z
X
X
Z
Z
Z
Z
Z
X
X
X
Z
H
X
Z
X
H
Z
Z
Z
Z
Z
Z
H
Z
X
H
X
L
X
X
Z
Z
L
H
H
L
L
H
L
L
L
X
X
X
Z
Z
L
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
L
H
H
H
H
L
H
L
H
see
Chapter 2.4.2
IN1 IN2 OUT1
OUT2 SF
1)
SPI
2)
DIA_REG
To limit the output current at low power loss, a chopper current limitation is integrated as
shown in
Figure 3.
The current is measured by sense cells integrated in the low-side
switches. As soon the current limit
I
L
is reached, the low-side switch is switched off for a
fixed time
t
a
.
current limit
I
L
I
OUT
off-time
t
a
time
Figure 3
Chopper current limitation
If Mode “Status-Flag” is selected (see
Chapter 2.4)
If Mode “SPI-Diagnosis” is selected (see
Chapter 2.4)
Table 2
Functional Truth Table
Preliminary Datasheet
5
V1.1, 2002-11-26
Preliminary Datasheet
6
V1.1, 2002-11-26
TLE 7209R
Circuit Description
TLE 7209R
Circuit Description
2.2.2
For 165
°C
<
T
j
< 175
°C
the current limit decreases from
I
L
= 6.6 A
±
1.1 A to
I
L
= 2.5 A
±
1.1 A as shown in
Figure 4
A
6.6A
Temperature-depending Current Limitation
2.3
Protection
The TLE 7209R is protected against short circuits, overload and invalid supply Voltage
by the following measures:
2.3.1
range of over-
temperature shut-
down
Short circuit to Ground
I
L
tolerance of
temperature dependent
current reduction
The high-side switches are protected against a short of the output to ground by an over
current shutdown. If a high-side switch is turned on and the current rises above the short
circuit detection current
I
OUK
all output transistors are turned off and the error bit “Short
Circuit to Ground on output 1 (2)”, SCG1 (SCG2) is stored in the internal status register.
2.5A
2.3.2
Short circuit to
V
S
Tj
165°C
175°C
°C
Figure 4
Temperature dependent current limitation
Due to the chopper current regulation, the low-side switches are already protected
against a short to the supply voltage.
To be able to distinguish a short circuit from normal
current limit operation, the current limitation is deactivated for the blanking time
t
b
after
the current has exceeded the current limit threshold
I
L
.
If the short circuit detection
current
I
OUK
is reached within this blanking time, a short circuit is detected (see
Figure 5).
All output transistors are turned OFF and the according error bit “Short Circuit
to Battery on output 1 (2)”, SCB1 (SCB2) is set.
IN
IN
I
OUK
t
b
I
L
I
OUT
t
a
I
OUK
t
b
t
b
I
L
time
I
OUT
time
Figure 5
Short to Vs detection. Left: normal operation. Right: short circuit is
detected
2.3.3
Short circuit across the load
If short circuit messages from high- and low-side switch occur simultaneously within a
delay time of typically 2µs, the error bit “Short Circuit Over Load”, SCOL is set.
Preliminary Datasheet
7
V1.1, 2002-11-26
Preliminary Datasheet
8
V1.1, 2002-11-26
TLE 7209R
Circuit Description
TLE 7209R
Circuit Description
2.3.4
In case of high DC-currents, insufficient cooling or high ambient temperature, the chip
temperature may rise above the thermal shutdown temperature
T
SD
. In that case, all
output transistors are shut down and the error-bit “Over-Temperature”, OT is set.
Over-Temperature
2.3.5
If the supply-voltage at the
V
S
pins falls below the under-voltage detection threshold, the
outputs are set to tristate and the error-bit “Under-Voltage at
V
S
“ is set.
Under-Voltage shutdown.
– In the SF-mode, all internal circuitry is supplied by the voltage on
V
S
. For that reason,
a loss of
V
S
supply voltage leads to a reset of all stored information (Power-ON-
Reset).
This Power-ON-Reset occurs as soon as under-Voltage is detected on
V
S
– In case of
short circuit, over-current or over-temperature,
the fault will be stored.
The output stage remains in tristate and the status-flag at low-level until the error is
reset by one of the following conditions: H -> L on DIS, L -> H on EN or Power-ON
Reset.
2.4.2
2.4.2.1
SPI-Mode (DMS = 5V)
SPI-Interface
2.4
The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag
Diagnosis. The choice of the Diagnosis-Mode is selected by the voltage-level on Pin 12
(DMS Diagnosis Mode Selection):
• DMS = GND, Status-Flag Mode
• DMS =
V
CC
, SPI-Diagnosis Mode
For the connection of Pins SDI, SDO, CSN and SCK/SF see
Figure 14
and
Figure 15.
Diagnosis
The serial SPI interface establishes a communication link between TLE 7209R and the
systems microcontroller. The TLE 7209R always operates in slave mode whereas the
controller provides the master function. The maximum baud rate is 2 MBaud (200pF on
SDO).
By applying an active slave select signal at CSN the TLE 7209R is selected by the SPI
master. SDI is the data input (Slave In), SDO the data output (Slave Out). Via SCK
(Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave
select signal (High) the data output SDO goes into tristate.
2.4.1
2.4.1.1
SF output
Status-Flag (SF) Mode (DMS = GND)
The first two bits of an instruction may be used to establish an extended device-
addressing. This gives the opportunity to operate up to 4 Slave-devices sharing one
common CSN signal from the Master-Unit (see
Figure 7)
In SF-mode, pin 2 is used as an open-drain output status-flag. The pin has to be pulled
to the logic supply voltage with a pull-up resistor, 47 kOhm recommended.
In case of any failure that leads to a shut-down of the outputs, the status-flag is set (e.g.
SF pin pulled to low). These failures are:
–
–
–
–
–
2.4.1.2
Fault storage and reset
Under Voltage on
V
S
Short circuit of OUT1 or OUT2 against
V
S
or GND
Short circuit between OUT1 and OUT2
Overcurrent
Overtemperature
DMS
SPI pow er-
supply
CSN
SCK
SPI-Control:
SDI
SDO
shift-register
-> state machine
-> clock counter
-> instruction recognition
– In case of
under-Voltage,
the failure is not latched. As soon as
V
S
falls below the
under-Voltage detection threshold, the output stage switches in tristate and the status-
flag is set from high level to low-level. If the voltage has risen above the specified value
again, the output stage switches on again and the status-flag is reset to high-level.
The Under Voltage failure is shown at the SF pin for
V
S
in the voltage range below the
detection threshold (typical 4.7V) down to 2.5V.
DIA_REG
Diagnosis
Figure 6
SPI block-diagram
Preliminary Datasheet
9
V1.1, 2002-11-26
Preliminary Datasheet
10
V1.1, 2002-11-26
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