PDSP16350
PDSP16350
I/Q Splitter/NCO
DS3711
ISSUE 2.3
September 1996
The PDSP16350 provides an integrated solution to the
need for very accurate, digitised, sine and cosine waveforms.
Both these waveforms are produced simultaneously, with 16
bit amplitude accuracy, and are synthesised using a 34 bit
phase accumulator. The more significant bits of this provide
16 bits of phase accuracy for the sine and cosine look up
tables.
With a 20 MHz system clock, waveforms up to 10 MHz can
be produced, with 0.001 Hz resolution. If frequency modula-
tion is required with no discontinuities, the phase increment
value can be changed linearly on every clock cycle. Alterna-
tively absolute phase jumps can be made to any phase value.
The provision of two output multipliers allows the sine and
cosine waveforms to be amplitude modulated with a 16 bit
value present on the input port. This option can also be used
to generate the in-phase and quadrature components from an
incoming signal. This I/Q split function is required by systems
which employ complex signal processing.
DIN
PHASE OFFSET
REGISTER
PHASE INCR
REGISTER
SCALING
REGISTER
ACCUM
MUX
PHASE ACCUM
REGISTER
CORDIC PROCESSOR ARRAY
FEATURES
s
s
s
s
s
Direct Digital Synthesiser producing simultaneous sine
and cosine values
16 bit phase and amplitude accuracy, giving spur levels
down to - 90 dB
Synthesised outputs from DC to 10 MHz with accuracies
better than 0.001 Hz
Amplitude and Phase modulation modes
84 pin PGA or 132 pin QFP
Fig. 1 Block Diagram
SIN
COS
APPLICATIONS
s
s
s
s
s
s
s
Numerically controlled oscillator (NCO)
Quadrature signal generator
FM, PM, or AM signal modulator
Sweep Oscillator
High density signal constellation applications with simul-
taneous amplitude and phase modulation
VHF reference for UHF generators
Signal demodulator
ASSOCIATED PRODUCTS
PDSP16256/A
PDSP16510A
PDSP16488A
Programmable FIR Filter
FFT Processor
2D Convolver
1
PDSP16350
SIGNAL
DESCRIPTION
DIN33:0
Data bus for the input register. This input register provides a 34 bit, incremental or absolute, phase
value, if the mode pin is low. Alternatively if the mode pin is high, it provides either an 18 bit phase
increment value, via D17:0, and a 16 bit scale value via D33:18 or a 34 bit phase increment value
depending on the JUMP input see below.
16 bit sine output data in fractional two’s complement format.
16 bit cosine output data in fractional two’s complement format.
Clock enable for the data input register. When low, data will be latched on the rising edge of the clock.
When high data will be retained in the input register.
Mode control input. When low, data in the input register is interpreted as either a 34 bit phase increment
value or a 34 bit absolute phase value. When high, the output multipliers are enabled and will scale the
waveforms with the upper 16 bits in the input register. The phase increment is loaded from the the lower
18 bits. The full 34 bit phase increment register can also be loaded using JUMP see below.
With MODE low (Frequency or Phase Modulation)
When low JUMP will allow normal phase incrementing to occur. When high, the data on the input pins
will be interpreted as a 34 bit absolute phase value to replace the present value in the accumulator.
JUMP is internally latched to match the delay through the data input register, and to allow data in the
internal pipeline to be correctly processed.
CEN
must also be low to latch the required data from DIN.
When Mode is high (Amplitude Modulation)
When low JUMP will allow normal phase incrementing to occur, with the phase increment value taken
from the lower 18 data inputs. When high, the data on the input pins will replace the full 34 bits of the
phase increment register.
CEN
must also be low to latch the required data.
SIN15:0
COS15:0
CEN
MODE
JUMP
RES
When high will clear the phase accumulator and phase increment registers, after data in the internal
pipeline has been correctly processed.
Input clock.
Output enable for SIN 15:0. Outputs are high impedance when
OES
is high.
Output enable for COS15:0. Outputs are high impedance when
OEC
is high.
Valid input flag. A delayed version of this input is available on the VOUT pin, with the delay matching
the data processing pipeline delay. This input has no other internal function.
Valid output flag. See above.
Five ground pins. All must be connected.
Four +5V pins. All must be connected.
CLK
OES
OEC
VIN
VOUT
GND
VCC
Table 1. Pin Description
4
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