PDSP16256/A datasheet, PDF - EEWORLD Datasheet

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PDSP16256/A: DescriptionI/Q Splitter/NCO; File Size159KB，13 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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PDSP16256/A Overview

I/Q Splitter/NCO

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Obsolescence Notice

This product is obsolete.

This information is available for your

convenience only.

For more information on

Zarlink’s obsolete products and

replacement product lists, please visit

http://products.zarlink.com/obsolete_products/

PDSP16350

SIGNAL

DESCRIPTION

DIN33:0

Data bus for the input register. This input register provides a 34 bit, incremental or absolute, phase

value, if the mode pin is low. Alternatively if the mode pin is high, it provides either an 18 bit phase

increment value, via D17:0, and a 16 bit scale value via D33:18 or a 34 bit phase increment value

depending on the JUMP input see below.

16 bit sine output data in fractional two’s complement format.

16 bit cosine output data in fractional two’s complement format.

Clock enable for the data input register. When low, data will be latched on the rising edge of the clock.

When high data will be retained in the input register.

Mode control input. When low, data in the input register is interpreted as either a 34 bit phase increment

value or a 34 bit absolute phase value. When high, the output multipliers are enabled and will scale the

waveforms with the upper 16 bits in the input register. The phase increment is loaded from the the lower

18 bits. The full 34 bit phase increment register can also be loaded using JUMP see below.

With MODE low (Frequency or Phase Modulation)

When low JUMP will allow normal phase incrementing to occur. When high, the data on the input pins

will be interpreted as a 34 bit absolute phase value to replace the present value in the accumulator.

JUMP is internally latched to match the delay through the data input register, and to allow data in the

internal pipeline to be correctly processed.

CEN

must also be low to latch the required data from DIN.

When Mode is high (Amplitude Modulation)

When low JUMP will allow normal phase incrementing to occur, with the phase increment value taken

from the lower 18 data inputs. When high, the data on the input pins will replace the full 34 bits of the

phase increment register.

CEN

must also be low to latch the required data.

SIN15:0

COS15:0

CEN

MODE

JUMP

RES

When high will clear the phase accumulator and phase increment registers, after data in the internal

pipeline has been correctly processed.

Input clock.

Output enable for SIN 15:0. Outputs are high impedance when

OES

is high.

Output enable for COS15:0. Outputs are high impedance when

OEC

is high.

Valid input flag. A delayed version of this input is available on the VOUT pin, with the delay matching

the data processing pipeline delay. This input has no other internal function.

Valid output flag. See above.

Five ground pins. All must be connected.

Four +5V pins. All must be connected.

CLK

OES

OEC

VIN

VOUT

GND

VCC

Table 1. Pin Description

PDSP16256/A Related Products

	PDSP16256/A	PDSP16488A	PDSP16350/A0/AC	PDSP16350/B0/AC	PDSP16350/B0/GC	PDSP16350/A0/GC
Description	I/Q Splitter/NCO	I/Q Splitter/NCO	I/Q Splitter/NCO	I/Q Splitter/NCO	I/Q Splitter/NCO	I/Q Splitter/NCO
Is it Rohs certified?	-	-	incompatible	incompatible	incompatible	incompatible
Maker	-	-	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)
package instruction	-	-	PGA, PGA84,13X13MOD	PGA, PGA84,13X13MOD	QFP, QFL132,.95SQ,25	QFP, QFL132,.95SQ,25
Reach Compliance Code	-	-	unknow	unknow	unknow	unknow
boundary scan	-	-	NO	NO	NO	NO
maximum clock frequency	-	-	20 MHz	20 MHz	20 MHz	20 MHz
External data bus width	-	-	34	34	34	34
JESD-30 code	-	-	S-CPGA-P84	S-CPGA-P84	S-CQFP-G132	S-CQFP-G132
JESD-609 code	-	-	e0	e0	e0	e0
length	-	-	27.94 mm	27.94 mm	24.13 mm	24.13 mm
low power mode	-	-	NO	NO	NO	NO
Number of terminals	-	-	84	84	132	132
Maximum operating temperature	-	-	125 °C	85 °C	85 °C	125 °C
Minimum operating temperature	-	-	-55 °C	-40 °C	-40 °C	-55 °C
Output data bus width	-	-	16	16	16	16
Package body material	-	-	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	-	-	PGA	PGA	QFP	QFP
Encapsulate equivalent code	-	-	PGA84,13X13MOD	PGA84,13X13MOD	QFL132,.95SQ,25	QFL132,.95SQ,25
Package shape	-	-	SQUARE	SQUARE	SQUARE	SQUARE
Package form	-	-	GRID ARRAY	GRID ARRAY	FLATPACK	FLATPACK
Peak Reflow Temperature (Celsius)	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	-	-	5 V	5 V	5 V	5 V
Certification status	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	-	4.14 mm	4.14 mm	3.58 mm	3.58 mm
Maximum supply voltage	-	-	5.5 V	5.5 V	5.25 V	5.5 V
Minimum supply voltage	-	-	4.5 V	4.5 V	4.75 V	4.5 V
Nominal supply voltage	-	-	5 V	5 V	5 V	5 V
surface mount	-	-	NO	NO	YES	YES
technology	-	-	CMOS	CMOS	CMOS	CMOS
Temperature level	-	-	MILITARY	INDUSTRIAL	INDUSTRIAL	MILITARY
Terminal surface	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	-	-	PIN/PEG	PIN/PEG	GULL WING	GULL WING
Terminal pitch	-	-	2.54 mm	2.54 mm	0.635 mm	0.635 mm
Terminal location	-	-	PERPENDICULAR	PERPENDICULAR	QUAD	QUAD
Maximum time at peak reflow temperature	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	-	-	27.94 mm	27.94 mm	24.13 mm	24.13 mm
uPs/uCs/peripheral integrated circuit type	-	-	DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR	DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR	DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR	DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR

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