ACT8342_08 datasheet, PDF - EEWORLD Datasheet

ACT8342

Rev0, 26-May-08

Three Channel Integrated Power Management IC

for Handheld Portable Equipment

FEATURES

•

Multiple Patents Pending

•

Three Integrated Regulators

−

350mA PWM Step-Down DC/DC

−

80mA Low Noise LDO

−

150mA Low Noise LDO

GENERAL DESCRIPTION

The patent-pending ACT8342 is a complete, cost

effective, highly-efficient

ActivePMU

TM

power man-

agement solution that is ideal for a wide range of

portable handheld equipment. This device inte-

grates one PWM step-down DC/DC converter and

two low noise, low dropout linear regulators (LDOs)

in a single, thin, space-saving package. This device

is ideal for a wide range of portable handheld

equipment that can benefit from the advantages of

ActivePMU

technology but does not require a high

level of integration.

REG1 is a fixed-frequency, current-mode PWM

step-down DC/DC converter that is optimized for

high efficiency and is capable of supplying up to

350mA output current. REG1’s output is available in

a variety of factory-preset output voltage options,

and an adjustable output voltage mode is also avail-

able. REG2, REG3 are low noise, high PSRR linear

regulators that are capable of supplying up to

80mA, and 150mA, respectively.

The ACT8342 is available in a tiny 3mm

×

3mm

16-pin Thin-QFN package that is just 0.75mm thin.

•

Independent Enable/Disable Control

•

Minimal External Components

•

3×3mm, Thin-QFN (TQFN33-16) Package

−

Only 0.75mm Height

−

RoHS Compliant

APPLICATIONS

•

Portable Devices and PDAs

•

MP3/MP4 Players

•

Wireless Handhelds

•

GPS Receivers, etc.

SYSTEM BLOCK DIAGRAM

REG1

Battery

nRSTO

nMSTR

nIRQ

ON1

ON2

ON3

Step-Down

DC/DC

OUT1

Adjustable, or

1.2V to 3.3V

Up to 350mA

OUT2

1.4V to 3.7V

Up to 80mA

OUT3

1.4V to 3.7V

Up to 150mA

System

Control

REG2

LDO

Pb

Pb-free

REG3

ACT8342

Active

LDO

PMU

TM

Innovative Power

TM

ActivePMU

TM

-1-

www.active-semi.com

is a trademark of Active-Semi.

ACT8342

FUNCTIONAL BLOCK DIAGRAM

Rev0, 26-May-08

OUT2

nRSTO

Active-Semi

ACT8342

VP1

To Battery

INL

REG1

nMSTR

SW1

FB1

GP1

OUT1

PUSH

BUTTON

OUT2

nIRQ

INL

ON1

ON2

ON3

REFBP

Reference

GA

REG2

LDO

To Battery or OUT1

System

Control

OUT2

REG3

LDO

OUT3

Innovative Power

TM

ActivePMU

TM

-2-

www.active-semi.com

is a trademark of Active-Semi.

ACT8342

ORDERING INFORMATION

PART

NUMBER

ACT8342QKCQI-T

Rev0, 26-May-08

V

OUT1

1.2V

V

OUT2

2.85V

V

OUT3

2.85V

PACKAGE

TQFN33-10

PINS

16

TEMPERATURE

RANGE

-40°C to +85°C

REG1 OUTPUT VOLTAGE CODES

A

Adjustable

C

1.2V

P

1.3V

J

1.4V

D

1.5V

E

1.8V

F

2.5V

I

2.8V

Q

2.85V

G

3.0V

H

3.3V

REG2 OUTPUT VOLTAGE CODES

J

1.4V

D

1.5V

L

1.7V

E

1.8V

F

2.5V

I

2.8V

Q

2.85V

G

3.0V

H

3.3V

REG3 OUTPUT VOLTAGE CODES

E

1.4V

G

1.5V

K

1.7V

M

1.8V

B

2.5V

H

2.8V

I

2.85V

L

3.0V

R

3.3V

: Output voltage options detailed in this table represent standard voltage options, and are available for samples or production orders.

Additional output voltage options, as detailed in the

Output Voltage Codes

table, are available for production subject to minimum order

quantities. Contact Active-Semi for more information regarding semi-custom output voltage combinations.

: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means

semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.

PIN CONFIGURATION

TOP VIEW

REGBP

ON3

15

GA

16

nIRQ

nMSTR

nRSTO

FB1

1

2

3

4

5

VP1

6

SW1

7

GP1

8

OUT2

GA

14

13

12

11

ON1

ON2

OUT3

INL

ACT8342

10

9

Thin - QFN (TQFN 33-16)

Innovative Power

TM

ActivePMU

TM

-3-

www.active-semi.com

is a trademark of Active-Semi.

ACT8342

PIN DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14, 16

15

Rev0, 26-May-08

NAME

nIRQ

nMSTR

nRSTO

OUT1

VP1

SW1

GP1

OUT2

INL

OUT3

ON2

ON1

REFBP

GA

ON3

DESCRIPTION

Open-Drain Push-Button Status Output. nIRQ is an open-drain output which sinks current

when nMSTR is asserted or when a fault-condition occurs. If interrupts are not masked.

Master Enable Input. Drive nMSTR to GA or to a logic low to enable the IC.

Open-Drain Reset Output. nRSTO asserts low for the reset timeout period of 300ms whenever

the IC is enabled.

Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the

internal feedback network to the output voltage.

Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close as

possible to the IC.

Switching node Output for REG1. Connect this pin to the switching end of the inductor.

Power Ground for REG1. Connect GA, GP1 together at a single point as close to the IC as

possible.

Output voltage for REG2. Capable of delivering up to 80mA of output current. Output has high

impedance when disabled.

Power input for REG2, REG3. Bypass to GA with a high quality ceramic capacitor placed as

close as possible to the IC.

Output voltage for REG3. Capable of delivering up to 150mA of output current. Output has

high impedance when disabled.

Enable Control Input for REG2. Drive ON2 to INL or to a logic high for normal operation, drive

to GA or a logic low to disable REG2.

Enable control input for REG1. Drive ON1 to the VP1 or a logic high for normal operation, drive

to GA or a logic low to disable REG1.

Reference Noise Bypass. Connect a 0.01µF ceramic capacitor from REFBP to GA. This pin is

discharged to GA in shutdown.

Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1 together at a

single point as close to the IC as possible.

Enable control input for REG3. Drive ON3 to the INL or a logic high for normal operation, drive

to GA or a logic low to disable REG3.

Innovative Power

TM

ActivePMU

TM

-4-

www.active-semi.com

is a trademark of Active-Semi.

ACT8342

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SW1 to GP1,

INL, VP1, FB1, OUT2, OUT3, ON1, ON2, ON3, nMSTR, nRSTO, nIRQ, REGBP to GA

SW1 to VP1

GP1 to GA

Junction to Ambient Thermal Resistance (θ

JA

)

Operating Temperature Range

Junction Temperature

Storage Temperature

Lead Temperature (Soldering, 10 sec)

Rev0, 26-May-08

VALUE

-0.3 to +6

-6 to +0.3

-0.3 to +0.3

33

-40 to 85

125

-55 to 150

300

UNIT

V

°C/W

°C

: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may

affect device reliability.

Innovative Power

TM

ActivePMU

TM

-5-

www.active-semi.com

is a trademark of Active-Semi.

ACT8342_08

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