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MAX3639

Description
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
File Size3MB,24 Pages
ManufacturerMaxim
Websitehttps://www.maximintegrated.com/en.html
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MAX3639 Overview

Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs

19-4911; Rev 0; 10/09
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
General Description
The MAX3639 is a highly flexible, precision phase-
locked loop (PLL) clock generator optimized for the next
generation of network equipment that demands low-jitter
clock generation and distribution for robust high-speed
data transmission. The device features subpicosecond
jitter generation, excellent power-supply noise rejection,
and pin-programmable LVDS/LVPECL output interfaces.
The MAX3639 provides nine differential outputs and
one LVCMOS output, divided into three banks. The fre-
quency and output interface of each output bank can be
individually programmed, making this device an ideal
replacement for multiple crystal oscillators and clock dis-
tribution ICs on a system board, saving cost and space.
This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN
package and operates from -40°C to +85°C.
S
Inputs
TION KIT
EVALUA BLE
AVAILA
Features
Crystal Interface: 18MHz to 33.5MHz
LVCMOS Input: 15MHz to 160MHz
Differential Input: 15MHz to 350MHz
Outputs
LVCMOS Output: Up to 160MHz
LVPECL/LVDS Outputs: Up to 800MHz
Three Individual Output Banks
Pin-Programmable Dividers
Pin-Programmable Output Interface
Wide VCO Tuning Range (3.60GHz to 4.025GHz)
Low Phase Jitter
0.34ps
RMS
(12kHz to 20MHz)
0.14ps
RMS
(1.875MHz to 20MHz)
Excellent Power-Supply Noise Rejection
-40NC to +85NC Operating Temperature Range
+3.3V Supply
MAX3639
S
S
S
S
S
S
S
Applications
Ethernet Switch/Router
Wireless Base Station
SONET/SDH Line Cards
PCIe
M
, Network
Processors
Fibre Channel SAN
Ordering Information
PART
MAX3639ETM+
TEMP RANGE
-40NC to +85NC
PIN-PACKAGE
48 TQFN-EP*
Typical Application Circuits and Pin Configuration appear at
end of data sheet.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Functional Diagram
LVPECL/LVDS
QA0
QA0
LVPECL/LVDS
QA1
QA1
LVPECL/LVDS
QA2
QA2
MAX3639
XOUT
XO
XIN
LVCMOS
CIN
PLL, DIVIDERS, MUXES
VCO
LVPECL/LVDS
LVPECL/LVDS
QA3
QA3
LVPECL/LVDS
QA4
QA4
QB0
QB0
LVPECL
DIN
DIN
LVPECL/LVDS
QB1
QB1
LVPECL/LVDS
QB2
QB2
LVPECL/LVDS
QC
QC
LVCMOS
QCC
PCIe is a registered trademark of PCI-SIG Corp.
_______________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

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