PR ELIMIN ARY
LM3S1911 Microcontroller
DATA SHE ET
DS-LM3S1911 - 42 8 3
Copyrig ht
©
2007-2008 Luminary Micro, Inc.
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Preliminary
November 17, 2008
LM3S1911 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 17
About This Document .................................................................................................................... 19
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
19
19
19
19
22
28
29
31
31
31
32
32
34
34
35
36
38
38
38
39
39
39
39
39
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 22
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 37
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 43
Interrupts ............................................................................................................................ 45
JTAG Interface .................................................................................................................... 48
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
49
49
49
51
52
52
55
55
55
57
6
6.1
6.1.1
System Control ................................................................................................................... 60
Functional Description ............................................................................................................... 60
Device Identification .................................................................................................................. 60
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Preliminary
3
Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ............................................................................................................................
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Register Access Timing ...........................................................................................................
Clock Source ..........................................................................................................................
Battery Management ...............................................................................................................
Real-Time Clock ......................................................................................................................
Non-Volatile Memory ...............................................................................................................
Power Control .........................................................................................................................
Initiating Hibernate ..................................................................................................................
Interrupts and Status ...............................................................................................................
Initialization and Configuration .................................................................................................
Initialization .............................................................................................................................
RTC Match Functionality (No Hibernation) ................................................................................
RTC Match/Wake-Up from Hibernation .....................................................................................
External Wake-Up from Hibernation ..........................................................................................
RTC/External Wake-Up from Hibernation ..................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
60
63
63
66
67
68
69
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
Hibernation Module .......................................................................................................... 119
120
120
120
121
122
122
123
123
123
124
124
124
124
125
125
125
125
126
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
Internal Memory ............................................................................................................... 139
Block Diagram ........................................................................................................................ 139
Functional Description ............................................................................................................. 139
SRAM Memory ........................................................................................................................ 139
Flash Memory ......................................................................................................................... 140
Flash Memory Initialization and Configuration ........................................................................... 141
Flash Programming ................................................................................................................. 141
Nonvolatile Register Programming ........................................................................................... 141
Register Map .......................................................................................................................... 142
Flash Register Descriptions (Flash Control Offset) ..................................................................... 143
Flash Register Descriptions (System Control Offset) .................................................................. 150
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 163
Functional Description ............................................................................................................. 163
Data Control ........................................................................................................................... 164
Interrupt Control ...................................................................................................................... 165
Mode Control .......................................................................................................................... 166
Commit Control ....................................................................................................................... 166
Pad Control ............................................................................................................................. 166
Identification ........................................................................................................................... 166
Initialization and Configuration ................................................................................................. 166
Register Map .......................................................................................................................... 168
Register Descriptions .............................................................................................................. 169
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Preliminary
November 17, 2008
LM3S1911 Microcontroller
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.4
10.5
General-Purpose Timers ................................................................................................. 204
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Bit Rate Generation .................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Frame Formats .......................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
204
205
206
206
207
211
211
212
212
213
213
214
214
215
241
241
242
242
243
265
265
265
266
267
267
268
268
269
269
269
270
271
305
306
306
306
306
307
314
315
316
11
11.1
11.2
11.3
11.4
11.5
Watchdog Timer ............................................................................................................... 240
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.2.8
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 264
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................ 305
14
14.1
Inter-Integrated Circuit (I
2
C) Interface ............................................................................ 342
Block Diagram ........................................................................................................................ 343
November 17, 2008
Preliminary
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FPGA/CPLD
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