PRELIMINARY
CLOCK GENERATOR FOR CAVIUM PROCESSORS
ICS840S06I
General Description
The ICS840S06I is a PLL-based clock generator
specifically designed for Cavium Networks SoC
HiPerClockS™
processors. This high performance device is
optimized to generate the processor core reference
clock, the DDR reference clocks, the PCI/PCI-X bus
clocks, and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs,
and edge rates that easily meet the input requirements for the
OCTEON processors. The output frequencies are generated from
a 25MHz external input source or an external 25MHz parallel
resonant crystal. The extended temperature range of the
ICS840S06I supports telecommunication, networking, and
storage requirements.
Features
•
Six LVCMOS/ LVTTL outputs, 20Ω typical output impedance
- One selectable core clock for the processor
- One selectable clock for the PCI/ PCI-X bus
- One 125MHz clock reference for GbE MAC
- Three 25MHz clock references for GbE PHY
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS,
LVHSTL, SSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Full 3.3V or mixed 3.3V core/2.5V output supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
ICS
•
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•
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Applications
•
•
Systems using OCTEON MIPS64 Broadband Processors
Networking, control and storage equipment, including routers,
switches, application-aware gateways, triple-play gateways,
WLAN and 3G/4G access and aggregation devices, storage
arrays, storage networking equipment, servers, and intelligent
NICs
802.11 a/b/g/n wireless for home data and multimedia
distribution
QoS for high quality Voice, Video, and Data service
Next-generationPON, VDSL2, and Cable networks
High-performance NAS
Audio/Video Storage and distribution
Consumer space media server
V
DD
nPLL_SEL
XTAL_IN
1
2
3
•
•
•
•
•
•
Pin Assignment
V
DDO_REF
QREF0
QREF1
QREF2
V
DDO_REF
GND
QC
V
DDO_C
32 31 30 29 28 27 26 25
24
V
DDO_B
QB
ICS840S06I
ICS8430S07I
32-Lead VFQFN
32-Lead VFQFN
5mm x 5mm x 0.75mm
5mm x 5mm x 0.75mm
package body
Package body
K Package
K Package
Top View
Top View
9
10 11 12 13 14 15 16
23
22
21
20
19
18
17
CORE_SEL
GND
GND
nOE_REF
XTAL_OUT 4
nXTAL_SEL
CLK
nCLK
GND
5
6
7
8
QA
V
DDO_A
PCI_SEL1
PCI_SEL0
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
CLOCK GENERATOR
1
ICS840S06AKI REV. AI JULY 10, 2008
V
DDA
V
DD
nc
nc
nc
nc
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 15
2
3,
4
5
6
7
8, 20, 21, 27
9,
10
11, 12, 13, 14
16
17
18, 23, 26, 29,
30, 31
Name
V
DD
nPLL_SEL
XTAL_IN,
XTAL_OUT
nXTAL_SEL
CLK
nCLK
GND
PCI_SEL1,
PCI_SEL0
nc
V
DDA
V
DDO_A
QA, QB, QC,
QREF2,
QREF1, QREF0
nOE_REF
Power
Input
Input
Input
Input
Input
Power
Input
Unused
Power
Power
Output
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Core supply pins.
PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, deselects
the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK)
input when HIGH. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Power supply ground.
Selects the PCI/PCI-X reference clock output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Bank A output supply pin. 3.3 V or 2.5V supply.
Single-ended outputs. LVCMOS/LVTTL interface levels.
Active LOW output enable. When logic HIGH, the outputs are in high
impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/
LVTTL interface levels.
Selects the processor core clock output frequency. The output frequency is
50MHz when LOW, and 33.333MHz when HIGH. See Table 3A.
LVCMOS/LVTTL interface levels.
Bank B output supply pin. 3.3 V or 2.5V supply.
Bank C output supply pin. 3.3 V or 2.5V supply.
REF bank output supply pins. 3.3 V or 2.5V supply.
19
Input
Pulldown
22
24
25
28, 32
CORE_SEL
V
DDO_B
V
DDO_C
V
DDO_REF
Input
Power
Power
Power
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
IDT™ / ICS™
CLOCK GENERATOR
3
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
(LVCMOS)
Outputs, I
O
(LVPECL)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
50mA
100mA
39.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO_X
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO_X
I
DD
I
DDA
I
DDO_X
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
–
0.16
3.135
Typical
3.3
3.3
3.3
140
16
20
Maximum
3.465
V
DD
3.465
Units
V
V
V
mA
mA
mA
NOTE: V
DDO_X
denotes V
DDO_B
, V
DDO_C
, V
DDO_D
and V
DDO_REF.
Table 4B. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO_X
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO_X
I
DD
I
DDA
I
DDO_X
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
–
0.16
2.375
Typical
3.3
3.3
2.5
130
16
16
Maximum
3.465
V
DD
2.625
Units
V
V
V
mA
mA
mA
NOTE: V
DDO_X
denotes V
DDO_B
, V
DDO_C
, V
DDO_D
and V
DDO_REF.
IDT™ / ICS™
CLOCK GENERATOR
5
ICS840S06AKI REV. AI JULY 10, 2008
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