Clock Generator for Cavium Processors
ICS8430S07I
DATA SHEET
General Description
The ICS8430S07I is a PLL-based clock generator
specifically designed for Cavium Networks SoC
HiPerClockS™
processors. This high performance device is optimized
to generate the processor core reference clock, the
DDR reference clocks, the PCI/PCI-X bus clocks, and
the clocks for both the Gigabit Ethernet MAC and PHY. The clock
generator offers ultra low-jitter, low-skew clock outputs, and edge
rates that easily meet the input requirements for the
CN3005/CN3010/CN3020 processors. The output frequencies are
generated from a 25MHz external input source or an external 25MHz
parallel resonant crystal. The extended temperature range of the
ICS8430S07I supports telecommunication, networking, and storage
requirements.
Features
•
•
One selectable differential LVPECL output pair for DDR
533/400/667
Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance
- One selectable core clock for the processor
- One selectable clock for the PCI/ PCI-X bus
- One 125MHz clock reference for GbE MAC
- Three 25MHz clock references for GbE PHY
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS,
LVHSTL, SSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.78ps (typical), QD output
Output supply:
LVPECL
– 3.3V Core
LVCMOS
– Core/Output
3.3V/3.3V
3.3V/2.5V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
ICS
•
•
•
•
•
Applications
•
•
Systems using CN30XX MIPS64 Broadband Processors
Networking, control and storage equipment, including routers,
switches, application-aware gateways, triple-play gateways,
WLAN and 3G/4G access and aggregation devices, storage
arrays, storage networking equipment, servers, and intelligent
NICs
802.11 a/b/g/n wireless for home data and multi-media distribution
QoS for high quality Voice, Video, and Data Service
Next-generation PON, VDSL2, and Cable Networks
High-performance NAS
Audio/Video Storage and Distribution
Consumer Space Media Server
•
•
•
V
DDO_REF
QREF0
QREF1
QREF2
V
DDO_REF
GND
32 31 30 29 28 27 26 25
V
DD
nPLL_SEL
XTAL_IN
XTAL_ OUT
nXTAL
_SEL
CLK
nCLK
GND
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
24
V
DDO_C
QC
ICS8430S07I
32- Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
QD
V
DDO_D
23
22
•
•
•
•
•
•
Pin Assignment
CORE
_SEL
21 GND
20
19
18
GND
MR/ nOE_ REF
QB
17 V
DDO_B
DDR_SEL1
DDR_SEL0
PCI_SEL1
nQA
QA
ICS8430S07AKI REVISION A SEPTEMBER 3, 2009
1
PCI_SEL0
©2009 Integrated Device Technology, Inc.
V
DDA
V
DD
ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Block Diagram
nPLL_SEL PD
nXTAL_SEL PD
00 = 133.333MHz
01 = 100.000MHz
10 = 83.333MHz
11 = 125.000MHz
DDR533, DDR400, or
QA
DDR667 Reference
nQA
Clock (LVPECL)
XTAL_IN
25MHz
XTAL_OUT
OSC
0
1
PLL
0 = 50.000MHz
1 = 33.333MHz
QB
Processor Core Clock
(LVCMOS)
0
1
00 = 133.333MHz
01 = 100.000MHz
10 = 66.667MHz
11 = 33.333MHz
125MHz GbE CLK
25MHz
CLK PD
nCLK PU/PD
QC
PCI or PCI-X Clock
(LVCMOS)
Gigabit Ethernet MAC
Clock (LVCMOS)
QD
DDR_SEL1:0 PD
CORE_SEL PD
PCI_SEL1:0 PD
MR/nOE_REF PD
QREF0
Clock Output
Control Logic
25MHz GbE CLK
\
\ Gigabit Ethernet
QREF1
/ PHY Clocks
/ (LVCMOS)
QREF2
ICS8430S07AKI REVISION A SEPTEMBER 3, 2009
2
©2009 Integrated Device Technology, Inc.
ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 1. Pin Descriptions
Number
1, 15
2
3, 4
5
6
7
8, 20, 21, 27
9, 10
11, 12
13, 14
16
17
18, 23, 26,
29, 30,
31
Name
V
DD
nPLL_SEL
XTAL_IN,
XTAL_OUT
nXTAL_SEL
CLK
nCLK
GND
PCI_SEL1,
PCI_SEL0
DDR_SEL1,
DDR_SEL0
nQA, QA
V
DDA
V
DDO_B
QB, QC, QD,
QREF2, QREF1,
QREF0
Power
Input
Input
Input
Input
Input
Power
Input
Input
Output
Power
Power
Output
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Core supply pins.
PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, bypasses
the PLL. LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK) input
when HIGH. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Power supply ground.
Selects the PCI/PCI-X reference clock output frequency. See Table 3C.
LVCMOS/LVTTL interface levels.
Selects the DDR reference clock output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
Bank B output supply pin. 3.3 V or 2.5V supply.
Single-ended outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the QREF[2:0] outputs are in high impedance
(HI-Z). When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/ LVTTL interface levels.
Selects the processor core clock output frequency. The output frequency is
50MHz when LOW, and 33.333MHz when HIGH. See Table 3A.
LVCMOS/LVTTL interface levels.
Bank C output supply pin. 3.3 V or 2.5V supply.
Bank D output supply pin. 3.3 V or 2.5V supply.
REF bank output supply pins. 3.3 V or 2.5V supply.
19
MR/nOE_REF
Input
Pulldown
22
24
25
28, 32
CORE_SEL
V
DDO_C
V
DDO_D
V
DDO_REF
Input
Power
Power
Power
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
ICS8430S07AKI REVISION A SEPTEMBER 3, 2009
3
©2009 Integrated Device Technology, Inc.
ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
V
DD,
V
DDO_X
= 3.465V
V
DD
= 3.465V, V
DDO_X
= 2.625V
Test Conditions
Minimum
Typical
2
4
4
51
51
V
DDO_X
= 3.465V
V
DDO_X
= 2.625V
15
20
Maximum
Units
pF
pF
pF
k
Ω
k
Ω
R
PULLDOWN
Input Pulldown Resistor
QB, QC, QD,
QREF[0:2]
QB, QC, QD,
QREF[0:2]
Ω
Ω
R
OUT
Output Impedance
NOTE: V
DDO_X
denotes V
DDO_B
, V
DDO_C
, V
DDO_D
and V
DDO_REF.
Function Tables
Table 3A. QB Output Control Input Function Table
Input
CORE_SEL
0 (default)
1
Output Frequency
QB
50MHz
33.333MHz
Table 3B. QA Output Control Input Function Table
Inputs
DDR_SEL1
0 (default)
0
1
1
DDR_SEL0
0 (default)
1
0
1
Output Frequency
QA, nQA
133.333MHz
100.000MHz
83.333MHz
125.000MHz
Table 3C. QC Output Control Input Function Table
Inputs
PCI_SEL1
0 (default)
0
1
1
PCI_SEL0
0 (default)
1
0
1
Output Frequency
QC
133.333MHz
100.000MHz
66.6667MHz
33.333MHz
ICS8430S07AKI REVISION A SEPTEMBER 3, 2009
4
©2009 Integrated Device Technology, Inc.
ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
(LVCMOS)
Outputs, I
O
(LVPECL)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
50mA
100mA
39.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO_X
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO_X
I
DD
I
DDA
I
DDO_X
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
–
0.20
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
170
20
25
Units
V
V
V
mA
mA
mA
NOTE: V
DDO_X
denotes V
DDO_B
, V
DDO_C
, V
DDO_D
and V
DDO_REF.
NOTE: I
DDO_X
= I
DDO_B
, I
DDO_C
, I
DDO_D
and I
DDO_REF.
Table 4B. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO_X
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO_X
I
DD
I
DDA
I
DDO_X
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
–
0.20
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
2.625
160
20
20
Units
V
V
V
mA
mA
mA
NOTE: V
DDO_X
denotes V
DDO_B
, V
DDO_C
, V
DDO_D
and V
DDO_REF.
NOTE: I
DDO_X
= I
DDO_B
, I
DDO_C
, I
DDO_D
and I
DDO_REF.
ICS8430S07AKI REVISION A SEPTEMBER 3, 2009
5
©2009 Integrated Device Technology, Inc.
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