Low Skew, 1-to-24, Differential-to-3.3V, 2.5V
LVPECL Fanout Buffer
ICS853S024
DATA SHEET
General Description
The ICS853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V
LVPECL Fanout Buffer. The PCLK, nPCLK pair can accept most
standard differential input levels. The ICS853S024 is characterized
to operate from either a 3.3V or a 2.5V power supply. Guaranteed
output skew characteristics make the ICS853S024 ideal for those
clock distribution applications demanding well defined performance
and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
Twenty four LVPECL outputs.
One differential clock input pair
Differential input clock (PCLK, nPCLK) can accept the following
signaling levels: LVDS, LVPECL, CML
Maximum output frequency: 2GHz
Translates any single ended input signal to 3.3V, 2.5V LVPECL
levels with resistor bias on nPCLK input
Output skew: 125ps (maximum)
Rise and Fall Time: 180ps (typical)
Additive phase jitter, RMS: 0.15ps (typical) @ 156.25MHz
Full 3.3V or 2.5V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLK
Pulldown
nPCLK
Pullup/Pulldown
24
24
Pin Assignment
Q23
nQ22
Q22
nQ[0:23]
V
CC
V
EE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
EE
V
CC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
3
46
4
45
ICS853S024
5
44
64-Lead TQFP, EPad
6
43
10mm x 10mm x 1mm
7
42
8
41
package body
9
40
Y Package
10
39
Top View
11
38
12
37
13
36
14
35
1
2
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
V
CC
V
EE
V
CC
Q6
V
EE
V
EE
Q[0:23]
nQ21
Q21
nQ20
V
CC
V
CC
nQ23
Q20
nQ19
Q19
nQ18
Q18
V
CC
nPCLK
PCLK
nQ17
Q17
nQ16
Q16
nQ15
Q15
nQ14
Q14
nQ13
Q13
nQ12
Q12
V
CC
V
CC
ICS853S024AY REVISION A JULY 20, 2011
1
©2011 Integrated Device Technology, Inc.
ICS853S024 Data Sheet
LOW SKEW, 1-TO-24, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 16, 18, 31,
33, 34, 50, 63, 64
2, 15, 17, 32, 49
3, 4
5, 6
7, 8
9, 10
11, 12
13, 14
19, 20
21, 22
23, 24
25, 26
27, 28
29, 30
35, 36
37, 38
39, 40
41, 42
43, 44
45, 46
47
48
51, 52
53, 54
55, 56
57, 58
59, 60
61, 62
Name
V
CC
V
EE
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
Q8, nQ8
Q9, nQ9
Q10, nQ10
Q11, nQ11
Q12, nQ12
Q13, nQ13
Q14, nQ14
Q15, nQ15
Q16, nQ16
Q17, nQ17
PCLK
nPCLK
Q18, nQ18
Q19, nQ19
Q20, nQ20
Q21, nQ21
Q22, nQ22
Q23, nQ23
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Type
Description
Power supply pins.
Negative supply pins.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left
floating.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS853S024AY REVISION A JULY 20, 2011
2
©2011 Integrated Device Technology, Inc.
ICS853S024 Data Sheet
LOW SKEW, 1-TO-24, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
32.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
240
Units
V
mA
Table 3B. LVPECL Differential DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
Input High Current
PCLK,
nPCLK
PCLK
I
IL
Input Low Current
nPCLK
V
PP
V
CMR
Peak-to-Peak Voltage
Common Mode Input Voltage;
NOTE 1
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
-10
-150
0.15
1.2
1.3
V
CC
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
Table 3C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: All outputs are terminated with 50Ω to V
CC
– 2V.
ICS853S024AY REVISION A JULY 20, 2011
3
©2011 Integrated Device Technology, Inc.
ICS853S024 Data Sheet
LOW SKEW, 1-TO-24, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
Table 3D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.6
1.0
Units
V
V
V
NOTE 1: All outputs are terminated with 50Ω to V
CC
– 2V.
AC Electrical Characteristics
Table 4. AC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
f
OUT
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Additive Phase Jitter, RMS;
Refer to Additive Phase Jitter
Section
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
47
180
156.25MHz,
Integration Range: 12kHz – 20MHz
312.5MHz,
Integration Range: 12kHz – 20MHz
400
0.15
0.11
75
125
200
300
53
Test Conditions
Minimum
Typical
Maximum
2
800
Units
GHz
ps
ps
ps
ps
ps
ps
%
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at f
OUT
≤
1GHz, unless otherwise noted.
NOTE: Special thermal considerations may be required. See Applications Section.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
ICS853S024AY REVISION A JULY 20, 2011
4
©2011 Integrated Device Technology, Inc.
ICS853S024 Data Sheet
LOW SKEW, 1-TO-24, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.15ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured usng a Rohde & Schwarz SMA100 as the input source.
ICS853S024AY REVISION A JULY 20, 2011
5
©2011 Integrated Device Technology, Inc.
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