Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS
Fanout Buffer
ICS8545I-02
DATASHEET
General Description
The ICS8545I-02 is a low skew, high performance
ICS
1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer
HiPerClockS™
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. Utilizing Low
Voltage Differential Signaling (LVDS) the ICS8545I-02
provides a low power, low noise, solution for distributing clock signals
over controlled impedances of 100Ω. The ICS8545I-02 accepts an
LVCMOS/LVTTL input level and translates it to 3.3V LVDS output
levels.
Guaranteed output and part-to-part skew characteristics make the
ICS8545I-02 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
Four differential LVDS output pairs
Two LVCMOS/LVTTL clock inputs to support redundant
or selectable frequency fanout applications
Maximum output frequency: 350MHz
Translates LVCMOS/LVTTL input signals to LVDS levels
Output skew: 60ps (maximum)
Part-to-part skew: 450ps (maximum)
Propagation delay: 1.45ns (maximum)
Additive phase jitter, RMS: 0.14ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN
Pullup
nD
Q
LE
CLK1
Pulldown
CLK2
Pulldown
CLK_SEL
Pulldown
0
0
1
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
OE
Pullup
Pin Assignment
GND
CLK_EN
CLK_SEL
CLK1
nc
CLK2
nc
OE
GND
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DD
Q1
nQ1
Q2
nQ2
GND
Q3
nQ3
ICS8545I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.925
mm
package body
G Package
Top View
ICS8545AGI-02 REVISION A JULY 29, 2009
1
©2009 Integrated Device Technology, Inc.
ICS8545I-02 Data Sheet
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 9, 13
2
Name
GND
CLK_EN
Power
Input
Pullup
Type
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input. When
LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK2 input.
When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
No connect.
Pulldown
Pullup
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
3
4
5, 7
6
8
10, 18
11, 12
14, 15
16, 17
19, 20
CLK_SEL
CLK1
nc
CLK2
OE
V
DD
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Unused
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS8545AGI-02 REVISION A JULY 29, 2009
2
©2009 Integrated Device Technology, Inc.
ICS8545I-02 Data Sheet
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
OE
0
1
1
1
1
CLK_EN
X
0
0
1
1
CLK_SEL
X
0
1
0
1
CLK1
CLK2
CLK1
CLK2
Selected Source
Q0:Q3
High-Impedance
Low
Low
Active
Active
Outputs
nQ0:nQ3
High-Impedance
High
High
Active
Active
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B.
Disabled
Enabled
CLK1, CLK2
CLK_EN
nQ[0:3]
Q[0:3]
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK1 or CLK2
0
1
Q0:Q3
LOW
HIGH
Outputs
nQ0:nQ3
HIGH
LOW
ICS8545AGI-02 REVISION A JULY 29, 2009
3
©2009 Integrated Device Technology, Inc.
ICS8545I-02 Data Sheet
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
91.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
90
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
CLK1, CLK2, CLK_SEL
OE, CLK_EN
CLK1, CLK2, CLK_SEL
OE, CLK_EN
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Table 4C. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.1
1.25
5
Test Conditions
Minimum
275
Typical
Maximum
525
50
1.4
50
Units
mV
mV
V
mV
ICS8545AGI-02 REVISION A JULY 29, 2009
4
©2009 Integrated Device Technology, Inc.
ICS8545I-02 Data Sheet
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle; NOTE 5
20% to 80%
ƒ
≤
166MHz
ƒ > 166MHz
150
45
40
155.52MHz, Integration Range:
12kHz – 20MHz
1.0
0.14
60
450
700
55
60
Test Conditions
Minimum
Typical
Maximum
350
1.45
Units
MHz
ns
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Measured using 50% duty cycle.
ICS8545AGI-02 REVISION A JULY 29, 2009
5
©2009 Integrated Device Technology, Inc.
京公网安备 11010802033920号
EEWORLD
