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EDI8F8257LP100BPI

Description
SRAM Module, 256KX8, 100ns, CMOS, SOIC-32
Categorystorage    storage   
File Size143KB,6 Pages
ManufacturerWhite Electronic Designs Corporation
Websitehttp://www.wedc.com/
Download Datasheet Parametric View All

EDI8F8257LP100BPI Overview

SRAM Module, 256KX8, 100ns, CMOS, SOIC-32

EDI8F8257LP100BPI Parametric

Parameter NameAttribute value
MakerWhite Electronic Designs Corporation
package instructionSOIC-32
Reach Compliance Codeunknown
Maximum access time100 ns
I/O typeCOMMON
JESD-30 codeR-XDMA-X32
memory density2097152 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of terminals32
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX8
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.54
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.000185 A
Minimum standby current2 V
Maximum slew rate0.13 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formUNSPECIFIED
Terminal pitch1.27 mm
Terminal locationDUAL
Base Number Matches1
EDI8F8257C
256Kx8 Static RAM CMOS, Module
FEATURES
• 256Kx8 bit CMOS Static
• Random Access Memory
• Access Times 70, 85 and 100ns
• Data Retention Function (LP version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
• High Density Packaging
DESCRIPTION
The EDI8F8257C is a 2Mb CMOS Static RAM based on two
128Kx8 Static RAMs mounted on a multi-layered epoxy laminate
(FR4) substrate.
Functional equivalence to the monolithic 2Mb Static RAM is
achieved by utilization of an on-board decoder that interprets the
higher order address (A17) to select one of the 128Kx8 Static
RAMs.
The 32 pin DIP pinout adheres to the JEDEC standard for the two
megabit device, to ensure compatibility with future monolithics.
The device is available with Low Power and Data Retention
(EDI8F8257LP).
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous, the EDI8F8257C requires
no clocks or refreshing for operation.
• 32 Pin SOIC Module, No. 21 (OBSOLETE)
• 32 Pin DIP Module, No. 184
• Single +5V (±10%) Supply Operation
PIN CONFIGURATIONS AND BLOCK DIAGRAM
OT
N
NS
SIG
DE
EW
RN
FO
ED
ND
ME
OM
EC
R
PIN NAMES
Address Inputs
Chip Enable
Write Enable
AØ-A17
E
W
G
DQØ-DQ7
VCC
VSS
NC
Output Enable
Common Data Input/Output
Power (+5V±10%)
Ground
No Connection
Sept. 2001 Rev. 9
ECO #14605
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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