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EDI88130LPSTM

Description
128Kx8 Monolithic SRAM, SMD 5962-89598
File Size204KB,9 Pages
ManufacturerETC
Download Datasheet View All

EDI88130LPSTM Overview

128Kx8 Monolithic SRAM, SMD 5962-89598

EDI88130CS
HI-RELIABILITY PRODUCT
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
s
Battery Back-up Operation
• 2V Data Retention (EDI88130LPS)
s
CS
1
, CS
2
& OE Functions for Bus Control
s
Inputs and Outputs Directly TTL Compatible
s
Organized as 128Kx8
s
Commercial, Industrial and Military Temperature Ranges
s
Thru-hole and Surface Mount Packages JEDEC Pinout
32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)
32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)
32 lead Ceramic SOJ (Package 140)
32 pad Ceramic Quad LCC (Package 12)
32 pad Ceramic LCC (Package 141)
32 lead Ceramic Flatpack (Package 142)
The EDI88130CS is a high speed, high performance, 128Kx8 bits
monolithic Static RAM.
An additional chip enable line provides system memory security
during power down in non-battery backed up systems and memory
banking in high speed battery backed systems where large mul-
tiple pages of memory are required.
The EDI88130CS has eight bi-directional input-output lines to
provide simultaneous access to all bits in a word.
A low power version, EDI88130LPS, offers a 2V data retention
function for battery back-up applications.
Military product is available compliant to MIL-PRF-38535.
*15ns access time is advanced information, contact factory for availability.
s
Single +5V (±10%) Supply Operation
FIG. 1
PIN CONFIGURATION
32 DIP
32 SOJ
32 CLCC
32 FLATPACK
32 QUAD LCC
PIN DESCRIPTION
I/O
0-7
A
0-16
WE
CS
1
, CS
2
29
28
27
26
25
24
23
22
21
TOP VIEW
A
12
A
14
A
16
NC
V
CC
A
15
CS
2
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V
±10%)
Ground
Not Connected
TOP VIEW
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
I/OØ
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 V
CC
31 A15
30 CS2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
4
3
2
1
32
31
30
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
1
I/O
7
OE
V
CC
V
SS
NC
BLOCK DIAGRAM
Memory Array
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
A
Ø-16
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
Ø-7
WE
CS
1
CS
2
OE
July 2001 Rev. 10
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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