ACS112D/SAMPLE-02 datasheet, PDF

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ACS112D/SAMPLE-02: DescriptionJ-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, DIP-16; Categorylogic logic; File Size196KB，3 Pages; ManufacturerHarris; Websitehttp://www.harris.com/

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ACS112D/SAMPLE-02 Overview

J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, DIP-16

ACS112D/SAMPLE-02 Parametric

Parameter Name	Attribute value
Maker	Harris
package instruction	DIP,
Reach Compliance Code	unknown
series	AC
JESD-30 code	R-CDIP-T16
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	16
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
propagation delay (tpd)	21 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
width	7.62 mm
Base Number Matches	1

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	ACS112D/SAMPLE-02	5962F9670401VXC	ACS112K/SAMPLE-02	ACS112D/SAMPLE	5962F9670401VEC	ACS112K/SAMPLE	ACS112HMSR
Description	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, DIP-16	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, DIP-16	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, DIP-16	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS
Maker	Harris	Harris	Harris	Harris	Harris	Harris	Harris
package instruction	DIP,	,	,	DIP,	DIP,	,	DIE,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
series	AC	AC	AC	AC	AC	AC	AC
JESD-30 code	R-CDIP-T16	R-CDFP-F16	R-CDFP-F16	R-CDIP-T16	R-CDIP-T16	R-CDFP-F16	X-XUUC-N16
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Number of digits	2	2	2	2	2	2	2
Number of functions	2	2	2	2	2	2	2
Number of terminals	16	16	16	16	16	16	16
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	UNSPECIFIED
Package form	IN-LINE	FLATPACK	FLATPACK	IN-LINE	IN-LINE	FLATPACK	UNCASED CHIP
propagation delay (tpd)	21 ns	21 ns	21 ns	21 ns	21 ns	21 ns	21 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	NO	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	THROUGH-HOLE	FLAT	FLAT	THROUGH-HOLE	THROUGH-HOLE	FLAT	NO LEAD
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	UPPER
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
encapsulated code	DIP	-	-	DIP	DIP	-	DIE
Base Number Matches	1	1	1	1	-	-	-

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