(Note 3) ....................................–0.3V to (V
DD
+ 0.3V)
Digital Input Voltages ................... – 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ...................– 0.3V to (V
DD
+ 0.3V)
Power Dissipation ...............................................100mW
Operation Temperature Range
LTC2356C-12/LTC2356C-14 .................... 0°C to 70°C
LTC2356I-12/LTC2356I-14 ...................– 40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
MSE PACKAGE
10-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 40°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
orDer inFormation
LEAD FREE FINISH
LTC2356CMSE-12#PBF
LTC2356IMSE-12#PBF
LTC2356CMSE-14#PBF
LTC2356IMSE-14#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
LTC2356CMSE-12#TRPBF LTCWN
LTC2356IMSE-12#TRPBF LTCWN
LTC2356CMSE-14#TRPBF LTCVF
LTC2356IMSE-14#TRPBF LTCVF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
converter characteristics
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Offset Error
Gain Error
Gain Tempco
(Notes 4, 5, 18)
(Notes 4, 18)
(Note 4, 18)
CONDITIONS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. With internal reference. V
DD
= 3.3V.
LTC2356-12
MIN
l
l
l
l
LTC2356-14
MAX
2
10
40
MIN
14
–4
–30
–80
TYP
±0.5
±2
±10
±15
±1
MAX
4
30
80
UNITS
Bits
LSB
LSB
LSB
ppm/°C
ppm/°C
TYP
±0.25
±1
±5
±15
±1
12
–2
–10
–40
Internal Reference (Note 4)
External Reference
2356fa
LTC2356-12/LTC2356-14
analog input
SYMBOL
V
IN
V
CM
I
IN
C
IN
t
ACQ
t
AP
t
JITTER
CMRR
PARAMETER
Analog Differential Input Range (Notes 3, 8, 9)
Analog Common Mode + Differential
Input Range (Note 10)
Analog Input Leakage Current
Analog Input Capacitance
Sample-and-Hold Acquisition Time
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
f
IN
= 1MHz, V
IN
= 0V to 3V
f
IN
= 100MHz, V
IN
= 0V to 3V
(Note 19)
(Note 6)
l
l
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference. V
DD
= 3.3V.
CONDITIONS
3.1V ≤ V
DD
≤ 3.6V
l
MIN
TYP
–1.25 to 1.25
0 to V
DD
MAX
UNITS
V
V
1
13
39
1
0.3
–60
–15
µA
pF
ns
ns
ps
dB
dB
Dynamic accuracy
SYMBOL
SINAD
THD
SFDR
IMD
PARAMETER
Signal-to-Noise Plus
Distortion Ratio
Total Harmonic
Distortion
Spurious Free
Dynamic Range
Intermodulation
Distortion
Code-to-Code
Transition Noise
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C with external reference = 2.55V. V
DD
= 3.3V. Single-ended A
IN+
signal drive with A
IN–
= 1.5V
DC. Differential signal drive with V
CM
= 1.5V at A
IN+
and A
IN–
LTC2356-12
CONDITIONS
100kHz Input Signal (Note 19)
1.4MHz Input Signal (Note 19)
100kHz First 5 Harmonics (Note 19)
1.4MHz First 5 Harmonics (Note 19)
100kHz Input Signal (Note 19)
1.4MHz Input Signal (Note 19)
0.625V
P-P
to 1.4MHz Summed with 0.625V
P-P
1.56MHz into A
IN+
and Inverted into A
IN–
V
REF
= 2.5V (Note 18)
l
l
LTC2356-14
MAX
MIN
70
–76
TYP
74.1
72.3
–86
–82
86
82
–82
1
50
5
–78
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
LSB
RMS
MHz
MHz
MIN
68
TYP
71.1
71.1
–86
–82
86
82
–82
0.25
50
5
Full Power Bandwidth V
IN
= 2.5V
P-P
, SDO = 11585LSB
P-P
(Note 15)
Full Linear Bandwidth S/(N + D) ≥ 68dB
internal reFerence characteristics
PARAMETER
V
REF
Output Voltage
V
REF
Output Tempco
V
REF
Line Regulation
V
REF
Output Resistance
V
REF
Settling Time
External V
REF
Input Range
V
DD
= 3.1V to 3.6V, V
REF
= 2.5V
Load Current = 0.5mA
C
REF
= 10µF
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 3.3V.
MIN
TYP
2.5
15
600
0.2
2
2.55
V
DD
MAX
UNITS
V
ppm/°C
µV/V
Ω
ms
V
2356fa
LTC2356-12/LTC2356-14
Digital inputs anD Digital outputs
SYMBOL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage D
OUT
Hi-Z Output Capacitance D
OUT
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
V
OUT
= 0V, V
DD
= 3.3V
V
OUT
= V
DD
= 3.3V
V
DD
= 3.3V, I
OUT
= –200µA
V
DD
= 3.1V, I
OUT
= 160µA
V
DD
= 3.1V, I
OUT
= 1.6mA
V
OUT
= 0V to V
DD
l
l
l
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 3.3V.
CONDITIONS
V
DD
= 3.6V
V
DD
= 3.1V
V
IN
= 0V to V
DD
l
l
l
MIN
2.4
TYP
MAX
0.6
±10
UNITS
V
V
µA
pF
V
V
V
µA
pF
mA
mA
5
2.5
2.9
0.05
0.10
1
20
15
0.4
±10
power requirements
SYMBOL
V
DD
I
DD
PARAMETER
Supply Voltage
Supply Current
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 17)
CONDITIONS
Active Mode
Nap Mode
Sleep Mode (LTC2356-12)
Sleep Mode (LTC2356-14)
Active Mode with SCK in Fixed State (Hi or Lo)
l
l
MIN
3.1
TYP
3.3
5.5
1.1
4
4
18
MAX
3.6
8
1.5
15
12
UNITS
V
mA
mA
µA
µA
mW
P
D
Power Dissipation
2356fa
LTC2356-12/LTC2356-14
timing characteristics
SYMBOL
PARAMETER
f
SAMPLE(MAX)
Maximum Sampling Rate per Channel
(Conversion Rate)
t
THROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period)
t
SCK
t
CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
12
Clock Period
Conversion Time
Minimum High or Low SCLK Pulse Width
CONV to SCK Setup Time
Nearest SCK Edge Before CONV
Minimum High or Low CONV Pulse Width
SCK↑ to Sample Mode
CONV↑ to Hold Mode
16th SCK↑ to CONV≠ Interval (Affects Acquisition Period)
Delay from SCK to Valid Data
SCK↑ to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
(Note 16)
(Note 6)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Note 14)
2
2
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3.3V.
CONDITIONS
l
l
l
MIN
3.5
TYP
MAX
UNITS
MHz
286
15.872
16
2
3
0
4
4
1.2
45
8
6
18
10000
ns
ns
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to GND.
Note 3:
When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4:
Offset and full-gain specifications are measured for a single-ended
A
IN+
input with A
IN–
grounded and using the internal 2.5V reference.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Recommended operating conditions.
Note 8:
The analog input range is defined for the voltage difference
between A
IN+
and A
IN–
. Performance is specified with A
IN–
= 1.5V DC while
driving A
IN+
.
Note 9:
The absolute voltage at A
IN+
and A
IN–
must be within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11:
Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13:
The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15:
The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5V
P-P
input sine wave.
Note 16:
Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock.
Note 17:
V
DD
= 3.3V, f
SAMPLE
= 3.5Msps.
Note 18:
The LTC2356-14 is measured and specified with 14-bit resolution
(1LSB = 152µV) and the LTC2356-12 is measured and specified with
12-bit resolution (1LSB = 610µV).
Note 19:
The sampling capacitor at each input accounts for 4.1pF of the
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FPGA/CPLD
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