S72WS256N based MCPs
Stacked Multi-Chip Product (MCP)
256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with 256/128 Megabit (4M/2M x 16-bit x 4 Banks) Mobile
SDRAM on Split Bus
ADVANCE
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
Flash burst frequency: 54 MHz
Mobile SDRAM burst frequency: 104 MHz
Package:
— 9.0 x 12.0 mm
Operating Temperature
— –25°C to +85°C (wireless)
High Performance
Flash access time: 70ns
General Description
The S72WS series is a product line of stacked Multi-Chip Product (MCP) packages
and consists of:
One or two (in this case, one die is used as code and the other as data) flash
memory dies
One Mobile SDRAM die
Separate bus for Flash and Mobile SDRAM: 137-ball pinout
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets for
further details:
Flash Memory Density
256Mb
Mobile
SDRAM
Density
128Mb
256Mb
S72WS256ND0
S72WS256NE0
512Mb
S72WS256NDE
S72WS256NEE
Publication Number
S72WS256N_00
Revision
A
Amendment
0
Issue Date
August 26, 2004
Product Selector Guide
Flash
Density
(Code)
Flash
Density
(Data)
Flash Initial/Burst
Speed (ns/MHz)
SDRAM SDRAM burst
Density Speed (MHz)
128
256 Mb
—
70ns/54MHz
256
104 MHz
Device-Model#
S72WS256ND0BAWB7
S72WS256ND0BAWBB
S72WS256NE0BAWB7
S72WS256NE0BAWBB
S72WS256NDEBAWU7
S72WS256NDEBAWUB
S72WS256NEEBAWU7
S72WS256NEEBAWUB
Supplier
1
2
1
2
1
DYB
Package
sector
9x12x1.2
unprotected
128
256 Mb 256 Mb
70ns/54MHz
256
104 MHz
2
1
2
sector
unprotected 9x12x1.4
2
S72WS256N based MCPs
S72WS256N_00A0 August 26, 2004
A d v a n c e
I n f o r m a t i o n
S72WS256N based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
High Performance ................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
MCP Block Diagram ............................................................................................. 7
Connection Diagram (2 x 256Mb Flash with 256Mb
SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Special Handling Instructions For FBGA Package ...................................8
Connection Diagram (2 x 256Mb Flash with 128Mb
SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Special Handling Instructions For FBGA Package ...................................9
Connection Diagram (256Mb Flash with 256Mb
SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Special Handling Instructions For FBGA Package ................................. 10
Connection Diagram (256MbFlash with 128Mb
SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Special Handling Instructions For FBGA Package .................................. 11
8-, 16-, and 32-Word Linear Burst without Wrap Around ............... 32
Configuration Register ...................................................................................... 32
RDY: Ready ...........................................................................................................32
Handshaking ......................................................................................................... 32
Simultaneous Read/Write Operations with Zero Latency ....................33
Writing Commands/Command Sequences .................................................33
Unlock Bypass Mode ......................................................................................33
Accelerated Program/Chip Erase Operations ............................................33
Write Buffer Programming Operation ........................................................ 34
Autoselect Mode ................................................................................................ 35
Advanced Sector Protection and Unprotection ....................................... 36
Persistent Mode Lock Bit ............................................................................. 36
Password Mode Lock Bit ............................................................................. 36
Sector Protection ............................................................................................... 37
Persistent Sector Protection ........................................................................... 37
Persistent Protection Bit (PPB) .................................................................. 38
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector
Protection Mode ............................................................................................ 38
Dynamic Protection Bit (DYB) .................................................................. 38
Table 13. Sector Protection Schemes ................................... 39
Lookahead Diagram on Split Bus . . . . . . . . . . . . . 12
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 13
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 15
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 17
TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA)
9 x 12.0 mm Package ...........................................................................................17
Password Sector Protection ...........................................................................40
64-bit Password ..............................................................................................40
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector
Protection Mode ............................................................................................40
Lock Register .......................................................................................................40
Table 14. WS256N Lock Register ......................................... 41
Table 15. WS128N/064N Lock Register ................................. 41
S29WSxxxN MirrorBit™ Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . . . 21
Product Selector Guide . . . . . . . . . . . . . . . . . . . . 24
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Block Diagram of
Simultaneous Operation Circuit . . . . . . . . . . . . . . 25
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .26
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .28
Table 1. Device Bus Operations ........................................... 28
Hardware Data Protection Mode ..................................................................41
Write Protect (WP#) ....................................................................................41
Low V
CC
Write Inhibit ................................................................................. 42
Write Pulse “Glitch” Protection ...............................................................42
Logical Inhibit ...................................................................................................42
Power-Up Write Inhibit ...............................................................................42
Standby Mode ......................................................................................................42
Automatic Sleep Mode .....................................................................................42
RESET#: Hardware Reset Input .....................................................................42
Output Disable Mode ....................................................................................... 43
SecSi™ (Secured Silicon) Sector Flash
Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Factory Locked: Factor SecSi Sector Programmed and Protected At
the Factory ....................................................................................................... 43
Table 16. SecSi
TM
Sector Addresses ...................................... 44
VersatileIO™ (V
IO
) Control ............................................................................ 28
Requirements for Asynchronous (Non-Burst)
Read Operation .................................................................................................. 28
Requirements for Synchronous (Burst) Read Operation ...................... 29
Table 2. Address Dependent Additional Latency ..................... 29
Table 3. Address Latency for x Wait States (≤ 80 MHz) ........... 29
Table 4. Address Latency for 6 Wait States (≤ 80 MHz) ........... 30
Table 5. Address Latency for 5 Wait States (≤ 68 MHz) ........... 30
Table 6. Address Latency for 4 Wait States (≤ 54 MHz) ........... 30
Table 7. Address Latency for 3 Wait States (≤ 40 MHz) ........... 30
Table 8. Address/Boundary Crossing Latency for 6 Wait States
(≤ 80 MHz) ....................................................................... 30
Table 9. Address/Boundary Crossing Latency for 5 Wait States
(< 68 MHz) ...................................................................... 31
Table 10. Address/Boundary Crossing Latency for 4 Wait States
(< 54 MHz) ...................................................................... 31
Table 11. Address/Boundary Crossing Latency for 3 Wait States
(< 40 MHz) ...................................................................... 31
Customer SecSi Sector ................................................................................. 44
Common Flash Memory Interface (CFI) . . . . . . 44
Table 17. CFI Query Identification String .............................. 45
Table 18. System Interface String ........................................ 45
Table 19. Device Geometry Definition................................... 45
Table 20. Primary Vendor-Specific Extended Query ................ 46
Table 21. WS256N Sector & Memory Address Map ................. 48
Table 22. WS128N Sector & Memory Address Map ................. 56
Table 23. WS064N Sector & Memory Address Map ................. 60
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 62
Reading Array Data ...........................................................................................62
Set Configuration Register Command Sequence .....................................62
Read Configuration Register Command Sequence .................................. 63
Figure 1. Synchronous/Asynchronous State Diagram.............. 63
Continuous Burst .............................................................................................31
8-, 16-, and 32-Word Linear Burst with Wrap Around .......................31
Table 12. Burst Address Groups .......................................... 32
Read Mode Setting ......................................................................................... 63
Programmable Wait State Configuration ............................................... 63
Table 24. Programmable Wait State Settings ......................... 64
Programmable Wait State ...........................................................................64
Boundary Crossing Latency ........................................................................64
August 26, 2004 S72WS256N_00A0
3
A d v a n c e
I n f o r m a t i o n
Table 25. Wait States for Handshaking ................................. 64
Figure 13. CLK Characterization........................................... 94
Handshaking .................................................................................................... 64
Burst Length Configuration ........................................................................ 64
Table 26. Burst Length Configuration ................................... 65
Synchronous/Burst Read .................................................................................. 95
Timing Diagrams .................................................................................................96
Figure 14. CLK Synchronous Burst Mode Read.......................
Figure 15. 8-word Linear Burst with Wrap Around ..................
Figure 16. 8-word Linear Burst without Wrap Around .............
Figure 17. Linear Burst with RDY Set One Cycle Before Data ...
96
97
97
98
Burst Wrap Around .......................................................................................65
RDY Configuration .........................................................................................65
RDY Polarity ....................................................................................................65
Configuration Register ......................................................................................66
Table 27. Configuration Register ......................................... 66
AC Characteristics—Asynchronous . . . . . . . . . . 99
Asynchronous Mode Read ..............................................................................99
Timing Diagrams .................................................................................................99
Figure 18. Asynchronous Mode Read with Latched Addresses .. 99
Figure 19. Asynchronous Mode Read .................................. 100
Reset Command ................................................................................................. 66
Autoselect Command Sequence ....................................................................67
Table 28. Autoselect Addresses ........................................... 68
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................ 68
Word Program Command Sequence .......................................................... 68
Figure 2. Word Program Operation ....................................... 69
Hardware Reset (RESET#) ............................................................................ 100
Figure 20. Reset Timings .................................................. 100
Erase/Program Timing .......................................................................................101
Figure 21. Asynchronous Program Operation Timings: WE#
Latched Addresses...........................................................
Figure 22. Synchronous Program Operation Timings:
CLK Latched Addresses ....................................................
Figure 23. Accelerated Unlock Bypass Programming Timing...
Figure 24. Data# Polling Timings
(During Embedded Algorithm)...........................................
Figure 25. Toggle Bit Timings
(During Embedded Algorithm)...........................................
Figure 26. Synchronous Data Polling Timings/
Toggle Bit Timings ...........................................................
Figure 27. DQ2 vs. DQ6 ...................................................
Figure 28. Latency with Boundary Crossing when
Frequency > 66 MHz........................................................
Figure 29. Latency with Boundary Crossing into Program/
Erase Bank .....................................................................
Figure 30. Example of Wait States Insertion........................
Figure 31. Back-to-Back Read/Write Cycle Timings ..............
102
103
104
104
105
105
106
106
107
108
109
Write Buffer Programming Command Sequence .................................... 69
Table 29. Write Buffer Command Sequence .......................... 70
Figure 3. Write Buffer Programming Operation ....................... 71
Unlock Bypass Command Sequence .........................................................72
Chip Erase Command Sequence ....................................................................72
Sector Erase Command Sequence .................................................................72
Figure 4. Erase Operation.................................................... 73
Erase Suspend/Erase Resume Commands ...................................................74
Program Suspend/Program Resume Commands ......................................74
Lock Register Command Set Definitions ....................................................75
Password Protection Command Set Definitions ......................................75
Non-Volatile Sector Protection Command Set Definitions ..................76
Figure 5. PPB Program/Erase Algorithm................................. 78
Global Volatile Sector Protection Freeze Command Set ......................79
Volatile Sector Protection Command Set ...................................................79
SecSi Sector Entry Command ........................................................................80
Command Definition Summary ...................................................................... 81
Table 30. Memory Array Commands ................................... 81
Table 31. Sector Protection Commands ................................ 82
Erase and Programming Performance . . . . . . . . 110
Write Operation Status . . . . . . . . . . . . . . . . . . . . .83
DQ7: Data# Polling ............................................................................................83
Figure 6. Data# Polling Algorithm......................................... 84
Mobile SDRAM Type 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . .
111
111
111
112
DQ6: Toggle Bit I ............................................................................................... 84
Figure 7. Toggle Bit Algorithm.............................................. 86
DQ2: Toggle Bit II .............................................................................................. 86
Table 32. DQ6 and DQ2 Indications ..................................... 87
Figure 32. Block Diagram ................................................. 112
Reading Toggle Bits DQ6/DQ2 ..................................................................... 87
DQ5: Exceeded Timing Limits ....................................................................... 87
DQ3: Sector Erase Start Timeout State Indicator ................................... 88
DQ1: Write to Buffer Abort ........................................................................... 88
Table 33. Write Operation Status ......................................... 89
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .90
Figure 8. Maximum Negative Overshoot Waveform ................. 90
Figure 9. Maximum Positive Overshoot Waveform .................. 90
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Functional Description . . . . . . . . . . . . . . . . . . . . . 113
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Mode Register Definition . . . . . . . . . . . . . . . . . . . 114
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 35. Burst Definition ................................................. 116
Figure 33. Mode Register Definition.................................... 117
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 90
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 91
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Figure 10. Test Setup ......................................................... 92
Table 34. Test Specifications ............................................... 92
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 34. CAS Latency .................................................... 118
Table 36. CAS Latency ..................................................... 118
Key to Switching Waveforms . . . . . . . . . . . . . . . 92
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 92
Figure 11. Input Waveforms and Measurement Levels............. 92
V
CC
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
AC Characteristics—Synchronous . . . . . . . . . . . 94
CLK Characterization ....................................................................................... 94
Figure 12. V
CC
Power-up Diagram ........................................ 93
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . 118
Extended Mode Register . . . . . . . . . . . . . . . . . . . 119
Temperature Compensated Self Refresh . . . . . 119
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . 119
Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 35. Extended Mode Register .................................... 120
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 37. Truth Table 1 - Commands and DQM Operation ..... 121
4
S72WS256N_00A0 August 26, 2004
A d v a n c e
I n f o r m a t i o n
Command Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . 121
No Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . 121
Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . 121
Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Burst Terminate . . . . . . . . . . . . . . . . . . . . . . . . . 123
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Deep Power-down . . . . . . . . . . . . . . . . . . . . . . . 124
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Bank/Row Activation ....................................................................................... 124
Figure 36. Activating a Specific Row in a Specific Bank Register....
125
Figure 37. Meeting t
RCD (MIN)
when 2 < t
RCD (MIN)
/t
CK
£
3....... 125
Figure 38. Read Command ................................................
Figure 39. Consecutive Read Bursts....................................
Figure 40. Random Read Accesses......................................
Figure 41. Read to Write ...................................................
Figure 42. Read to Write with Extra Clock Cycle ...................
Figure 43. Read to Precharge.............................................
Figure 44. Terminating a Read Burst...................................
Figure 45. Write Command................................................
Figure 46. Write Burst.......................................................
Figure 47. Write to Write...................................................
Figure 48. Random Write Cycles.........................................
Figure 49. Write to Read ...................................................
Figure 50. Write to Precharge ............................................
127
128
128
129
130
130
131
132
133
133
134
134
135
Reads ..................................................................................................................... 125
Table 45. IDD Specifications and Conditions ........................ 150
Table 46. I
DD7
— Self Refresh Current Options .................... 151
Table 47. Capacitance ...................................................... 151
Figure 60. Initialize and Load Mode Register........................ 152
Figure 61. Power Down Mode ............................................ 153
Figure 62. Clock Suspend Mode ......................................... 154
Figure 63. Auto Refresh Mode ........................................... 155
Figure 64. Self Refresh Mode............................................. 156
Figure 65. Read - Without Auto Precharge .......................... 157
Figure 66. Read - With Auto Precharge ............................... 158
Figure 67. Single Read - Without Auto Precharge ................. 159
Figure 68. Single Read - With Auto Precharge ..................... 160
Figure 69. Alternating Bank Read Accesses ......................... 161
Figure 70. Read - Full-Page Burst ...................................... 162
Figure 71. Read - DQM Operation ...................................... 163
Figure 72. Write - Without Auto Precharge .......................... 164
Figure 73. Write - With Auto Precharge .............................. 165
Figure 74. Single Write - Without Auto Precharge ................ 166
Figure 75. Single Write with Auto Precharge........................ 167
Figure 76. Alternating Bank Write Accesses......................... 168
Figure 77. Write - Full Page Burst ...................................... 169
Figure 78. Write - DQM Operation...................................... 170
Mobile SDRAM Type 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . .
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
AC Operating Test Conditions . . . . . . . . . . . . . .
171
171
172
172
173
173
Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 79. DC Output Load Circuit...................................... 174
Figure 80. AC Output Load Circuit...................................... 174
Precharge ..............................................................................................................135
Power-down ........................................................................................................135
Figure 51. Power-Down..................................................... 136
Figure 52. Terminating a Write Burst .................................. 136
Figure 53. Precharge Command ......................................... 136
Deep Power-down ............................................................................................137
Clock Suspend .....................................................................................................137
Burst Read/Single Write ..................................................................................137
Figure 54. Clock Suspend During Write Burst ....................... 138
Figure 55. Clock Suspend During Read Burst ....................... 138
Concurrent Auto Precharge ......................................................................... 138
Read with Auto Precharge ......................................................................... 138
Figure 56. Read with Auto precharge Interrupted by a Read .. 139
Figure 57. Read with Auto Precharge Interrupted by a Write .. 139
Operating AC Parameter . . . . . . . . . . . . . . . . . . 175
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 176
Simplified Truth Table . . . . . . . . . . . . . . . . . . . . . 177
Mode Register Field Table to Program Modes . 178
Normal MRS Mode . . . . . . . . . . . . . . . . . . . . . . . . 178
EMRS for PASR (Partial Array Self Ref.) & DS
(Driver Strength) . . . . . . . . . . . . . . . . . . . . . . . . . 179
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . 179
Internal Temperature Compensated Self Refresh
(TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 180
Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Burst Length = 4 ............................................................................................... 180
Burst Length = 8 ............................................................................................... 180
Write with Auto Precharge ........................................................................... 139
Figure 58. Write with Auto Precharge Interrupted by a Read .. 140
Figure 59. Write with Auto Precharge Interrupted by a Write.. 140
Table 38. Truth Table 2—CKE ............................................141
Table 39. Truth Table 3 — Current State Bank n, Command to Bank
n ....................................................................................142
Table 40. Truth Table 4 — Current State Bank n, Command to Bank
m ...................................................................................144
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . 181
Addresses of 64Mb ............................................................................................181
Bank Addresses (BA0 ~ BA1) .....................................................................181
Address Inputs (A0 ~ A11) ...........................................................................181
Addresses of 128Mb ...........................................................................................181
Bank Addresses (BA0 ~ BA1) .....................................................................181
Address Inputs (A0 ~ A11) ..........................................................................182
Clock .....................................................................................................................182
Clock Enable (CKE) ..........................................................................................182
NOP and Device Deselect .............................................................................182
DQM Operation ................................................................................................182
Mode Register Set (MRS) ................................................................................183
Extended Mode Register Set (EMRS) ..........................................................183
Bank Activate ......................................................................................................183
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 146
Table 41. DC Electrical Characteristics and Operating
Conditions .......................................................................146
Table 42. AC Electrical Characteristics and Operating
Conditions .......................................................................146
Table 43. Electrical Characteristics and Recommended AC
Operating Conditions ........................................................147
Table 44. AC Functional Characteristics ...............................149
August 26, 2004 S72WS256N_00A0
5
MCU
京公网安备 11010802033920号
EEWORLD
