KSZ8851SNLTR datasheet, PDF - EEWORLD Datasheet

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KSZ8851SNLTR: DescriptionDATACOM, ETHERNET TRANSCEIVER, QCC32, 5 X 5 MM, LEAD FREE, QFN-32; CategoryWireless rf/communication Telecom circuit; File Size639KB，80 Pages; ManufacturerMicrel ( Microchip ); Websitehttps://www.microchip.com; Environmental Compliance

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KSZ8851SNLTR Overview

DATACOM, ETHERNET TRANSCEIVER, QCC32, 5 X 5 MM, LEAD FREE, QFN-32

KSZ8851SNLTR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	QFN
package instruction	HVQCCN,
Contacts	32
Reach Compliance Code	compliant
JESD-30 code	S-XQCC-N32
JESD-609 code	e4
length	5 mm
Humidity sensitivity level	2
Number of functions	1
Number of terminals	32
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	0.9 mm
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5 mm
Base Number Matches	1

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KSZ8851SNL/SNLI

Single-Port Ethernet Controller

with SPI Interface

Rev. 2.0

General Description

The KSZ8851SNL is a single-chip Fast Ethernet controller

consisting of a 10/100 physical layer transceiver (PHY), a

MAC, and a Serial Peripheral Interface (SPI). The

KSZ8851SNL is designed to enable an Ethernet network

connectivity with any host micro-controller equipped with

SPI interface. The KSZ8851SNL offers the most cost-

effective solution for adding high-throughput Ethernet link

to traditional embedded systems with SPI interface.

The KSZ8851SNL is a single chip, mixed analog/digital

device offering Wake-on-LAN technology for effectively

addressing Fast Ethernet applications. It consists of a Fast

Ethernet MAC controller, SPI interface and incorporates a

unique dynamic memory pointer with 4-byte buffer

boundary and a fully utilizable 18KB for both TX (allocated

6KB) and RX (allocated 12KB) directions in host buffer

interface.

The KSZ8851SNL is designed to be fully compliant with

the appropriate IEEE 802.3 standards. An industrial

temperature-grade version of the KSZ8851SNL, the

KSZ8851SNLI is also available (see “Ordering Information”

section).

LinkMD

Physical signal transmission and reception are enhanced

through the use of analog circuitry, making the design

more efficient and allowing for lower-power consumption.

The KSZ8851SNL is designed using a low-power CMOS

process that features a single 3.3V power supply with

options for 1.8V, 2.5V or 3.3V VDD I/O. The device

includes an extensive feature set that offers management

information base (MIB) counters and a fast SPI interface

with clock speed up to 40MHz.

The KSZ8851SNL includes unique cable diagnostics

feature called LinkMD . This feature determines the length

of the cabling plant and also ascertains if there is an open

or short condition in the cable. Accompanying software

enables the cable length and cable conditions to be

conveniently displayed. In addition, the KSZ8851SNL

supports Hewlett Packard (HP) Auto-MDIX thereby

eliminating the need to differentiate between straight or

crossover cables in applications.

Functional Diagram

Figure 1. KSZ8851SNL/SNLI Functional Diagram

LinkMD is a registered trademark of Micrel, Inc.

Magic Packet is a trademark of Advanced Micro Devices, Inc.

MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.

Product names used in this datasheet are for identification purposes

only and may be trademarks of their respective companies.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (

408

) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

August 2009

M9999-083109-2.0

Micrel, Inc.

KSZ8851SNL/SNLI

Contents

Pin Configuration ................................................................................................................................................................ 10

Pin Description .................................................................................................................................................................... 11

Strapping Options ............................................................................................................................................................... 12

Functional Description ....................................................................................................................................................... 13

Functional Overview ........................................................................................................................................................... 13

Power Management........................................................................................................................................................ 13

Normal Operation Mode........................................................................................................................................... 13

Energy Detect Mode ................................................................................................................................................ 13

Soft Power Down Mode ........................................................................................................................................... 14

Power Saving Mode ................................................................................................................................................. 14

Wake-on-LAN ................................................................................................................................................................. 14

Detection of Energy.................................................................................................................................................. 14

Detection of Linkup .................................................................................................................................................. 14

Wake-up Packet....................................................................................................................................................... 15

Magic Packet............................................................................................................................................................ 15

Physical Layer Transceiver (PHY).................................................................................................................................. 16

100BASE-TX Transmit .............................................................................................................................................. 16

100BASE-TX Receive ............................................................................................................................................... 16

PLL Clock Synthesizer (Recovery)............................................................................................................................. 16

Scrambler/De-scrambler (100BASE-TX only) ............................................................................................................ 16

10BASE-T Transmit .................................................................................................................................................. 16

10BASE-T Receive ................................................................................................................................................... 16

MDI/MDI-X Auto Crossover...................................................................................................................................... 17

Straight Cable .................................................................................................................................................... 17

Crossover Cable ................................................................................................................................................ 17

Auto Negotiation....................................................................................................................................................... 18

LinkMD Cable Diagnostics ..................................................................................................................................... 19

Access

............................................................................................................................................................... 19

Usage

................................................................................................................................................................ 20

Media Access Control (MAC) Operation ........................................................................................................................ 20

Inter Packet Gap (IPG)............................................................................................................................................. 20

Back-Off Algorithm ................................................................................................................................................... 20

Late Collision............................................................................................................................................................ 20

Flow Control ............................................................................................................................................................. 20

Half-Duplex Backpressure ....................................................................................................................................... 21

Address Filtering Function ....................................................................................................................................... 21

Clock Generator ....................................................................................................................................................... 22

Serial Peripheral Interface (SPI) ..................................................................................................................................... 22

SPI Internal I/O Registers Access Operation Timing............................................................................................... 23

SPI TXQ/RXQ FIFOs Access Operation Timing...................................................................................................... 23

Queue Management Unit (QMU).................................................................................................................................... 24

Transmit Queue (TXQ) Frame Format..................................................................................................................... 24

Frame Transmitting Path Operation in TXQ ............................................................................................................ 25

August 2009

M9999-083109-2.0

Micrel, Inc.

KSZ8851SNL/SNLI

Driver Routine for Transmit Packet from Host Processor to KSZ8851SNL............................................................. 26

Receive Queue (RXQ) Frame Format ..................................................................................................................... 29

Frame Receiving Path Operation in RXQ ................................................................................................................ 29

Driver Routine for Receive Packet from KSZ8851SNL to Host Processor.............................................................. 30

EEPROM Interface ......................................................................................................................................................... 31

Loopback Support........................................................................................................................................................... 32

Near-end (Remote) Loopback.................................................................................................................................. 32

Far-end (Local) Loopback

........................................................................................................................................ 32

SPI Interface to I/O Registers............................................................................................................................................. 33

I/O Registers................................................................................................................................................................... 33

Internal I/O Registers Space Mapping............................................................................................................................ 34

Register Map: MAC, PHY and QMU................................................................................................................................... 40

Bit Type Definition........................................................................................................................................................... 40

0x00 – 0x07: Reserved................................................................................................................................................... 40

Chip Configuration Register (0x08 – 0x09): CCR .......................................................................................................... 40

0x0A – 0x0F: Reserved .................................................................................................................................................. 40

Host MAC Address Registers: MARL, MARM and MARH ............................................................................................. 40

Host MAC Address Register Low (0x10 – 0x11): MARL................................................................................................ 41

Host MAC Address Register Middle (0x12 – 0x13): MARM........................................................................................... 41

Host MAC Address Register High (0x14 – 0x15): MARH .............................................................................................. 41

0x16 – 0x1F: Reserved .................................................................................................................................................. 41

On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................... 41

EEPROM Control Register (0x22 – 0x23): EEPCR ....................................................................................................... 42

Memory BIST Info Register (0x24 – 0x25): MBIR .......................................................................................................... 42

Global Reset Register (0x26 – 0x27): GRR ................................................................................................................... 43

0x28 – 0x29: Reserved................................................................................................................................................... 43

Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................... 43

0x2C – 0x2F: Reserved .................................................................................................................................................. 43

Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ........................................................................................ 43

Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ........................................................................................ 44

Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ................................................................................ 44

Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ................................................................................ 44

Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ................................................................................ 44

Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3................................................................................ 44

0x3C – 0x3F: Reserved .................................................................................................................................................. 45

Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ........................................................................................ 45

Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ........................................................................................ 45

Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ................................................................................ 45

Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ................................................................................ 45

Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ................................................................................ 45

Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3................................................................................ 45

0x4C – 0x4F: Reserved .................................................................................................................................................. 46

Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ........................................................................................ 46

Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ........................................................................................ 46

Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ................................................................................ 46

August 2009

M9999-083109-2.0

KSZ8851SNLTR Related Products

	KSZ8851SNLTR	KSZ8851SNLITR
Description	DATACOM, ETHERNET TRANSCEIVER, QCC32, 5 X 5 MM, LEAD FREE, QFN-32	DATACOM, ETHERNET TRANSCEIVER, QCC32, 5 X 5 MM, LEAD FREE, QFN-32
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Parts packaging code	QFN	QFN
package instruction	HVQCCN,	HVQCCN,
Contacts	32	32
Reach Compliance Code	compliant	compliant
JESD-30 code	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e4	e4
length	5 mm	5 mm
Humidity sensitivity level	2	2
Number of functions	1	1
Number of terminals	32	32
Maximum operating temperature	70 °C	85 °C
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260
Certification status	Not Qualified	Not Qualified
Maximum seat height	0.9 mm	0.9 mm
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Telecom integrated circuit types	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	40
width	5 mm	5 mm
Base Number Matches	1	1

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