CY7C1386D_11 datasheet, PDF - EEWORLD Datasheet

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CY7C1386D_11: Description18-Mbit (512 K x 36/1 M x 18) Pipelined DCD Sync SRAM; File Size938KB，36 Pages; ManufacturerCypress Semiconductor

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CY7C1386D_11 Overview

18-Mbit (512 K x 36/1 M x 18) Pipelined DCD Sync SRAM

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CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

18-Mbit (512 K × 36/1 M × 18) Pipelined

DCD Sync SRAM

18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM

Features

■

Functional Description

The

CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

SRAM

[1]

integrates 512 K × 36/1 M × 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive edge triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining chip enable (CE

), depth expansion

chip enables (CE

and CE

3 [2]

), burst control inputs (ADSC,

ADSP, and ADV), write enables (BW

, and BWE), and global

write (GW). Asynchronous inputs include the output enable (OE)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see

on page 4

and

Truth Table on page 11

for further

details). Write cycles can be one to four bytes wide as controlled

by the byte write control inputs. GW active LOW causes all bytes

to be written. This device incorporates an additional pipelined

enable register which delays turning off the output buffers an

additional cycle when a deselect is executed.This feature allows

depth expansion without penalizing system performance.

The

CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

operates from a +3.3 V core power supply while all outputs

operate with a +3.3 V or +2.5 V supply. All inputs and outputs are

JEDEC-standard and JESD8-5-compatible.

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 167 MHz

Registered inputs and outputs for pipelined operation

Optimal for performance (double-cycle deselect)

Depth expansion without wait state

3.3 V core power supply (V

)

2.5 V or 3.3 V I/O power supply (V

DDQ)

Fast clock-to-output times

❐

2.6 ns (for 250 MHz device)

Provides high performance 3-1-1-1 access rate

User selectable burst counter supporting Intel





Pentium



Interleaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self-timed writes

Asynchronous output enable

CY7C1386D/CY7C1387D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA

package. CY7C1386F/CY7C1387F available in Pb-free and

non Pb-free 119-ball BGA package

IEEE 1149.1 JTAG-compatible boundary scan

ZZ sleep mode option

■

Selection Guide

Description

Maximum access time

Maximum operating current

Maximum CMOS standby current

250 MHz

2.6

350

200 MHz

3.0

300

167 MHz

3.4

275

Unit

Notes

1. For best practices or recommendations, please refer to the Cypress application note

AN1064,

SRAM System Design Guidelines

www.cypress.com.

2. CE

and CE

are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable.

Cypress Semiconductor Corporation

Document Number: 38-05545 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised July 12, 2011

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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