CY8C21634, CY8C21534, CY8C21434
CY8C21334, CY8C21234
PSoC
®
Programmable System-on-Chip™
PSoC
®
Programmable System-on-Chip™
Features
■
Powerful Harvard-architecture processor
❐
M8C processor speeds up to 24 MHz
❐
Low power at high speed
❐
Operating voltage: 2.4 V to 5.25 V
❐
Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐
Industrial temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC
®
blocks)
❐
Four analog Type E PSoC blocks provide:
• Two comparators with digital-to-analog converter (DAC)
references
• Single or dual 10-bit 28 channel analog-to-digital
converters (ADC)
❐
Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receiver transmitter
(UART), serial peripheral interface (SPI) master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐
Complex peripherals by combining blocks
Flexible on-chip memory
❐
8 KB flash program storage 50,000 erase/write cycles
❐
512 bytes static random access memory (SRAM) data
storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
EEPROM emulation in flash
Complete development tools
❐
Free development software
(PSoC Designer™)
❐
Full-featured, in-circuit emulator (ICE) and programmer
❐
Full-speed emulation
❐
Complex breakpoint structure
❐
128-KB trace memory
Precision, programmable clocking
❐
Internal ±2.5% 24- / 48-MHz main oscillator
❐
Internal oscillator for watchdog and sleep
Programmable pin configurations
❐
25-mA sink, 10-mA source on all GPIOs
❐
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐
Up to eight analog inputs on GPIOs
❐
Configurable interrupt on all GPIOs
■
Versatile analog mux
❐
Common internal analog bus
❐
Simultaneous connection of I/O combinations
❐
Capacitive sensing application capability
Additional system resources
2
❐
I C master, slave, and multi-master to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable low-voltage detection (LVD)
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
■
■
Logic Block Diagram
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 38-12025 Rev. *V
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 21, 2010
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CY8C21634, CY8C21534, CY8C21434
CY8C21334, CY8C21234
Contents
PSoC® Programmable System-on-Chip™ ..................... 1
Features ............................................................................. 1
Logic Block Diagram ........................................................ 1
PSoC Functional Overview .............................................. 3
The PSoC Core ........................................................... 3
The Digital System ...................................................... 3
The Analog System ..................................................... 4
Additional System Resources ..................................... 4
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules .............................................. 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pin Information ................................................................. 8
16-Pin Part Pinout ....................................................... 8
20-Pin Part Pinout ....................................................... 9
28-Pin Part Pinout ..................................................... 10
32-Pin Part Pinout ..................................................... 11
56-Pin Part Pinout ..................................................... 13
Register Reference ......................................................... 15
Register Conventions ................................................ 15
Register Mapping Tables .......................................... 15
Electrical Specifications ................................................ 18
Absolute Maximum Ratings ....................................... 18
Operating Temperature ............................................. 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 25
Packaging Information ................................................... 33
Thermal Impedances ................................................. 37
Solder Reflow Peak Temperature ............................. 37
Development Tool Selection ......................................... 38
Software .................................................................... 38
Development Kits ...................................................... 38
Evaluation Tools ........................................................ 38
Device Programmers ................................................. 39
Accessories (Emulation and Programming) .............. 39
Ordering Information ...................................................... 40
Ordering Code Definitions ......................................... 41
Acronyms ........................................................................ 42
Reference Documents .................................................... 42
Document Conventions ................................................. 43
Units of Measure ....................................................... 43
Numeric Conventions ................................................ 43
Glossary .......................................................................... 43
Document History Page ................................................. 48
Sales, Solutions, and Legal Information ...................... 50
Worldwide Sales and Design Support ....................... 50
Products .................................................................... 50
PSoC Solutions ......................................................... 50
Document Number: 38-12025 Rev. *V
Page 2 of 50
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PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
The PSoC architecture, shown in
Figure 1,
consists of four main
areas: the core, the system resources, the digital system, and
the analog system. Configurable global bus resources allow
combining all of the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 GPIOs are also included. The GPIOs provide
access to the global digital and analog interconnects.
The Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that is used alone or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■
■
■
■
■
■
■
■
■
■
PWMs (8- to 32-bit)
PWMs with dead band (8- to 32-bit)
Counters (8- to 32-bit)
Timers (8- to 32-bit)
UART 8- with selectable parity
Serial peripheral interface (SPI) master and slave
I
2
C slave and multi-master
CRC/generator (8-bit)
IrDA
PRS generators (8-bit to 32-bit)
The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO) and internal low speed oscillator (ILO). The CPU
core, called the M8C, is a powerful processor with speeds up to
24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
System resources provide these additional capabilities:
■
■
■
■
■
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in
Table 1 on page 5.
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
Digital clocks for increased flexibility
I
2
C functionality to implement an I
2
C master and slave
An internal voltage reference, multi-master, that provides an
absolute value of 1.3 V to a number of PSoC subsystems
A SMP that generates normal operating voltages from a single
battery cell
Various system resets supported by the M8C
Digital Clocks
To System Bus
From Core
To Analog
System
Row Input
Configuration
The analog system consists of four analog PSoC blocks,
supporting comparators, and analog-to-digital conversion up to
10 bits of precision.
8
8
DBB00
DBB01
DCB02
DCB03
4
Row Output
Configuration
The digital system consists of an array of digital PSoC blocks that
may be configured into any number of digital peripherals. The
digital blocks are connected to the GPIOs through a series of
global buses. These buses can route any signal to any pin,
freeing designs from the constraints of a fixed peripheral
controller.
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 38-12025 Rev. *V
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The Analog System
The analog system consists of four configurable blocks that allow
for the creation of complex analog signal flows. Analog
peripherals are very flexible and can be customized to support
specific application requirements. Some of the common PSoC
analog functions for this device (most available as user modules)
are:
■
■
■
■
The Analog Multiplexer System
The analog mux bus can connect to every GPIO pin. Pins may
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8:1
analog input multiplexer provides a second path to bring Port 0
pins to the analog array.
Switch-control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
ADCs (single or dual, with 8-bit or 10-bit resolution)
Pin-to-pin comparator
Single-ended comparators (up to two) with absolute (1.3 V)
reference or 8-bit DAC reference
1.3-V reference (as a system resource)
Track pad, finger sensing
Chip-wide mux that allows analog input from any I/O pin
Crosspoint connection between any I/O pin combinations
In most PSoC devices, analog blocks are provided in columns of
three, which includes one continuous time (CT) and two switched
capacitor (SC) blocks. The CY8C21x34 devices provide limited
functionality Type E analog blocks. Each column contains one
CT Type E block and one SC Type E block. Refer to the
PSoC
Technical Reference Manual
for detailed information on the
CY8C21x34’s Type E analog blocks.
Figure 2. Analog System Block Diagram
Additional System Resources
System resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch-mode pump,
low-voltage detection, and power-on-reset (POR).
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
The I
2
C module provides 100- and 400-kHz communication
over two wires. Slave, master, and multi-master modes are all
supported.
LVD interrupts can signal the application of falling voltage
levels, while the advanced POR circuit eliminates the need for
a system supervisor.
An internal 1.3-V reference provides an absolute reference for
the analog system, including ADCs and DACs.
An integrated switch-mode pump generates normal operating
voltages from a single 1.2-V battery cell, providing a low cost
boost converter.
Versatile analog multiplexer system.
Array Input
Configuration
■
■
ACI0[1:0]
All I/O
X
X
X
X
ACI1[1:0]
■
■
ACOL1MUX
Analog Mux Bus
■
X
Array
ACE00
ASE10
ACE01
ASE11
Document Number: 38-12025 Rev. *V
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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks.
Table 1
lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is
highlighted in
Table 1.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
CY8C28xxx
CY8C27x43
CY8C24x94
CY8C24x23A
CY8C23x33
CY8C22x45
CY8C21x45
CY8C21x34
CY8C21x23
CY8C20x34
CY8C20xx6
Digital
I/O
up to 64
up to 44
up to 44
up to 56
up to 24
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
Digital
Rows
4
up to 3
2
1
1
1
2
1
1
1
0
0
Digital
Blocks
16
up to 12
8
4
4
4
8
4
4
4
0
0
Analog
Inputs
up to 12
up to 44
up to 12
up to 48
up to 12
up to 12
up to 38
up to 24
up to 28
up to 8
up to 28
up to 36
Analog
Outputs
4
up to 4
4
2
2
2
0
0
0
0
0
0
Analog
Columns
4
up to 6
4
2
2
2
4
4
2
2
0
0
Analog
Blocks
12
up to
12 + 4
[1]
12
6
6
4
6
[1]
6
[1]
4
[1]
SRAM
Size
2K
1K
256
1K
256
256
1K
512
512
256
512
up to
2K
Flash
Size
32 K
16 K
16 K
16 K
4K
8K
16 K
8K
8K
4K
8K
up to
32 K
4
[1]
3
[1,2]
3
[1,2]
Getting Started
For in-depth information, along with detailed programming
details, see the
PSoC
®
Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest
PSoC device datasheets
on the web.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the
CYPros Consultants
web site.
Application Notes
Cypress application notes
are an excellent introduction to the
wide variety of possible PSoC designs.
Solutions Library
Visit our growing
library of solution focused designs.
Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Development Kits
PSoC Development Kits
are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Technical Support
Technical support
– including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Training
Free PSoC technical training
(on demand, webinars, and
workshops), which is available online via
www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
Notes
1. Limited analog functionality
.
2. Two analog blocks and one CapSense
®
.
Document Number: 38-12025 Rev. *V
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