LFSW35105-100 datasheet, PDF - EEWORLD Datasheet

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LFSW35105-100: DescriptionINTELLIGENT INTERACTIVE SYNTHESIZER; CategoryAnalog mixed-signal IC The signal circuit; File Size437KB，7 Pages; ManufacturerSYNERGY; Websitehttp://www.synergymwave.com/; Environmental Compliance

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LFSW35105-100 Overview

INTELLIGENT INTERACTIVE SYNTHESIZER

LFSW35105-100 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SYNERGY
Parts packaging code	QFN
package instruction	ROHS COMPLIANT, SMT-44
Contacts	44
Reach Compliance Code	compli
Analog Integrated Circuits - Other Types	PLL FREQUENCY SYNTHESIZER
JESD-30 code	R-XQCC-N44
length	49.53 mm
Number of functions	1
Number of terminals	44
Maximum operating temperature	75 °C
Minimum operating temperature	-30 °C
Package body material	UNSPECIFIED
encapsulated code	QCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	11.938 mm
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	COMMERCIAL EXTENDED
Terminal form	NO LEAD
Terminal pitch	2.54 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	31.75 mm

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INTELLIGENT INTERACTIVE SYNTHESIZER

SURFACE MOUNT MODEL:

LFSW35105-100

WIDE BANDWIDTH

FEATURES:

►

Exceptionally Low Phase Noise

►

Interactive Communication

►

Standard Programming Interface

►

Ultra Wide Tuning Range

►

Lead Free - RoHS Compliant

►

Patent Pending REL-PRO

Technology

►

Small Size, Surface Mount

►

Buffered Output

Phase Noise

-40

-50

-60

-70

Phase Noise (dBc/Hz)

350 - 1050 MHz

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

100

1000

10000

100000

1000000

10000000

Offset Frequency (Hz)

350.000 MHz / 15.2 dBm

700.000 MHz / 14.8 dBm

1050.00 MHz / 11.5 dBm

SPECIFICATIONS (Rev. F 08/07/07)

Frequency

Step Size

Reference

Input Frequency

Reference

Input Voltage

Bias Voltage

Output Power

Spurious Suppression

Harmonic Suppression

Settling Time

Output Impedance

Typical Phase Noise

350 - 1050 MHz

1000 kHz

10 MHz*

1 V p-p to 3.3 V p-p

Vcc

Digital

VCO

Converter

Analog

+10 dBm (Min.)

85 dB (Typ.)

20 dB (Typ.)

10 mSec (Typ.)**

50 Ohms

Offset

@ 1 kHz

@ 10 kHz

@ 100 kHz

V (Vdc)

I (mA Max.)

Package #

280LF

Phase Noise

-100 dbc/Hz

-102 dbc/Hz

-132 dbc/Hz

Operating

-30 to +75 °C

Temperature Range

Programming

See Application Note: AN7100

* Reference input frequency is programmable in multiples of the step size, 10 MHz

is the default setting with 150 MHz (Max.).

** From the rising edge of LE to stable lock detect.

Absolute Maximum Ratings

Storage Temp. Range

Bias Voltage (Digital)

Bias Voltage (VCO)

Bias Voltage (Converter)

Bias Voltage (Analog)

DC Voltage Applied to RF Out

-55 to +125 ºC

+5.25 V

+5.5 V

+8 V

+5.25 V

±25 V

Pin 6 - RF Out

Pin 8 - Ref In

Pin 9 - Vcc(VCO) ****

Pin 10 - Vcc(Converter) ****

Pin 12 - Lock Detect Out*

Pin 14 - Vcc(Tune) ***

Pin 16 - Vout(Converter) ***

Pin 25 - Latch Enable In

Pin 26 - Data In

Pin 27 - Error Flag

Pin 28 - Clock In

Pin 29 - Reset **

Pin 34 - Vcc(Digital) ****

Pin 36 - Vtune

Pin-Out

Pin 38 - Vcc(Analog) ****

Pin 19-22, 24, 30-33 - NC

All Others Ground

NC - No Connection

* High when locked (source/sink 500 uA)

** A low on this input will reset the internal controller. Leave unconnected for

normal operation.

*** Connect pins 14 and 16 together externally and add 10uF tantalum bypass

capacitor to ground.

**** Supply external ﬁltering for pin 9, 10, 34 and 38

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