Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
F
EATURES
•
Fully integrated PLL
•
17 LVCMOS/LVTTL outputs, 15Ω typical output impedance
•
Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
•
Maximum output frequency: 166.67MHz
•
Maximum crystal input frequency: 38MHz
•
Maximum REF_CLK input frequency: 83.33MHz
•
Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz simultaneously
•
Separate feedback control for generating PCI / PCI-X
frequencies from a 20MHz or 25MHz crystal or 33.333MHz
or 66.666MHz reference frequency
•
Cycle-to-cycle jitter: 70ps (maximum)
•
Period jitter, RMS: 17ps (maximum)
•
Output skew: 230ps (maximum)
•
Bank skew: 40ps (maximum)
•
Static phase offset: 0 ± 150ps (maximum)
G
ENERAL
D
ESCRIPTION
The ICS8761 is a low voltage, low skew PCI /
PCI-X Clock Generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8761 has a selectable
REF_CLK or crystal input. The REF_CLK input
accepts LVCMOS or LVTTL input levels. The ICS8761 has a
fully integrated PLL along with frequency configurable clock
and feedback outputs for multiplying and regenerating clocks
with “zero delay”. Using a 20MHz or 25MHz crystal or a
33.333MHz or 66.666MHz reference frequency, the ICS8761
will generate output frequencies of 33.333MHz, 66.666MHz,
100MHz and 133.333MHz simultaneously.
ICS
The low impedance LVCMOS/LVTTL outputs of the ICS8761
are designed to drive 50Ω series or parallel terminated
transmission lines.
B
LOCK
D
IAGRAM
OEA
MR
D_SELA0
D_SELA1
REF_CLK
XTAL1
OSC
1
0
÷3
÷4
÷6
÷12
00
01
10
11
•
Full 3.3V or 3.3V core, 2.5V multiple output supply modes
•
0°C to 85°C ambient operating temperature
•
Lead-Free package available
QA0
QA1
0
1
P
IN
A
SSIGNMENT
V
DDOC
V
DDOC
V
DDOD
V
DDOD
GND
GND
GND
GND
QC0
QC1
QC2
QC3
QD0
QD1
QD2
QA3
REF_CLK
1
2
3
4
5
6
7
8
9
XTAL2
XTAL_SEL
FB_IN
PLL_SEL
OEB
D_SELB1
D_SELB0
PLL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
QD3
QA2
GND
FB_OUT
V
DDOFB
FB_IN
V
DD
FBDIV_SEL0
FBDIV_SEL1
MR
V
DD
D_SELD0
D_SELD1
OED
OEB
D_SELB0
D_SELB1
GND
00
01
10
11
QB0
QB1
QB2
QB3
GND
XTAL1
XTAL2
V
DD
XTAL_SEL
PLL_SEL
V
DDA
QC0
OEC
00
01
10
11
QC1
ICS8761
41
40
39
38
37
36
35
34
D_SELC1
D_SELC0
OED
00
01
10
11
V
DD
QC2
D_SELC0
QC3
D_SELC1
OEC
OEA
D_SELA0
D_SELA1
GND
10
11
12
13
14
15
QD0
QD1
QD2
QD3
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
QA0
QA1
QA2
QA3
QB0
QB1
QB2
V
DDOA
V
DDOA
V
DDOB
V
DDOB
GND
GND
GND
GND
QB3
D_SELD1
D_SELD0
÷6
÷12
÷16
÷20
00
01
10
11
FB_OUT
FBDIV_SEL1
FBDIV_SEL0
8761CY
64-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
www.icst.com/products/hiperclocks.html
1
REV. C SEPTEMBER 7, 2004
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
Type
Input
Power
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 16, 17,
21, 25, 29,
33, 48, 52,
56, 60, 64
3, 4
5, 9, 40, 44
6
7
8
10, 11
12
13
14, 15
18, 20,
22, 24
19, 23
26, 28,
30, 32
27, 31
34, 35
36
37
38, 39
Name
REF_CLK
GND
XTAL1,
XTAL2
V
DD
XTAL_SEL
PLL_SEL
V
DDA
D_SELC0,
D_SELC1
OEC
OEA
D_SELA0,
D_S E LA 1
QA0, QA1,
QA2, QA3
V
DDOA
QB0, QB1,
QB2, QB3
V
DDOB
D_SELB1,
D_SELB0
OEB
OE D
D_SELD1,
D_SELD0
MR
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Power supply ground.
Input
Power
Input
Input
Power
Input
Input
Input
Input
Output
Power
Output
Power
Input
Input
Input
Input
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pullup
Pullup
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Core supply pins.
Selects between crystal oscillator or reference clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects REF_CLK
when LOW. LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
Analog supply pin. See Applications Note for filtering.
Selects divide value for Bank C outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines state of Bank C outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank A outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank A outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Bank A clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank A outputs.
Bank B clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank B outputs.
Selects divider value for Bank B outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines state of Bank B outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank D outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank D outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Active HIGH Master reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with "zero
delay". LVCMOS / LVTTL interface levels.
41
Input
Pulldown
42
43
45
FBDIV_SEL1
FBDIV_SEL0
FB_IN
Input
Input
Input
Pulldown
Pullup
Pulldown
8761CY
www.icst.com/products/hiperclocks.html
2
REV. C SEPTEMBER 7, 2004
Integrated
Circuit
Systems, Inc.
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
Type
Power
Output
Output
Power
Output
Power
Description
Output supply pin for FB_Out output.
Feedback output. Connect to FB_IN. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Bank D clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank D outputs.
Bank C clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank C outputs.
Number
46
47
49, 51,
53, 55
50, 54
57, 59,
61, 63
58, 62
Name
V
DDOFB
FB_OUT
QD3, QD2,
QD1, QD0
V
DDOD
QC3, QC2,
QC1, QC0
V
DDOC
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output); NOTE 1
Output Impedance
V
DD
, V
DDA
= 3.465V; V
DDOx
= 3.465V
V
DD
, V
DDA
= 3.465V; V
DDOx
= 2.625V
15
Test Conditions
Minimum Typical
Maximum
4
51
51
9
11
Units
pF
KΩ
KΩ
pF
pF
Ω
NOTE 1: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, V
DDOD
, V
DDOFB
.
T
ABLE
3A. O
UTPUT
C
ONTROL
P
IN
F
UNCTION
T
ABLE
Inputs
MR
1
0
X
OEA
1
1
0
OEB
1
1
0
OEC
1
1
0
OED
1
1
0
QA0:QA3
LOW
Active
HiZ
LOW
Active
HiZ
Outputs
QB0:QB3
QC0:QC3
LOW
Active
HiZ
QD0:QD3
LOW
Active
HiZ
T
ABLE
3B. O
PERATING
M
ODE
F
UNCTION
T
ABLE
Inputs
PLL_SEL
0
1
Operating Mode
Bypass
PLL
T
ABLE
3C. PLL I
NPUT
F
UNCTION
T
ABLE
Inputs
XTAL_SEL
0
1
PLL Input
REF_CLK
XTAL Oscillator
8761CY
www.icst.com/products/hiperclocks.html
3
REV. C SEPTEMBER 7, 2004
Integrated
Circuit
Systems, Inc.
T
ABLE
3D. C
ONTROL
F
UNCTION
T
ABLE
Inputs
Reference
Frequency Range
(MHz)
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
Outputs
PLL_SEL =1
QX0:QX3
x2
x4
x 5.33
x 6.67
x 1.5
x3
x4
x5
x1
x2
x 2.67
x 3.33
÷2
÷1
x 1.33
Frequency
QX0:QX3
(MHz)
83.33 - 166.67
83.33 - 166.67
83.33 - 166.67
83.33 - 166.67
62.4 - 125
62.4 - 125
62.4 - 125
62.4 - 125
41.6 - 83.33
41.6 - 83.33
41.6 - 83.33
41.6 - 83.33
20.8 - 41.67
20.8 - 41.67
20.8 - 41.67
FB_OUT
(MHz)
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
D_SELx1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
D_SELx0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
FBDIV_SEL1 FBDIV_SEL0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
12.5 - 25
x 1.67
20.8 - 41.67
12.5 - 25
NOTE: D_SELX1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELX0 denotes D_SELA0, D_SELB0,
D_SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
T
ABLE
3E. C
ONTROL
F
UNCTION
T
ABLE
(PCI C
ONFIGURATION
)
Inputs
D_SELx1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
D_SELx0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
FBDIV_SEL1 FBDIV_SEL0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Reference Frequency
(MHz)
66.67
33.33
25
20
66.67
33.33
25
20
66.67
33.33
25
20
66.67
33.33
25
Outputs
PLL_SEL = 1
QX0:QX3
x2
x4
x 5.33
x 6.67
x 1.5
x3
x4
x5
x1
x2
x 2.67
x 3.33
÷2
÷1
x 1.33
Frequency
QX0:QX3
FB_OUT
(MHz)
(MHz)
133
66.67
133
133
133
100
100
100
100
66.67
66.67
66.67
66.67
33.33
33.33
33.33
33.33
25
20
66.67
33.33
25
20
66.67
33.33
25
20
66.67
33.33
25
1
1
1
1
20
x 1.67
33.33
20
NOTE: D_SELx1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELx0 denotes D_SELA0, D_SELB0,
D_SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
8761CY
www.icst.com/products/hiperclocks.html
4
REV. C SEPTEMBER 7, 2004
Integrated
Circuit
Systems, Inc.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDOx
+ 0.5V
41.1°C/W (0 lfpm)
-65°C to 150°C
ICS8761
L
OW
V
OLTAGE
, L
OW
S
KEW
,
PCI / PCI-X C
LOCK
G
ENERATOR
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDOX
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDOx
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
175
55
25
Units
V
V
V
mA
mA
mA
Output Supply Current; NOTE 2
I
DDOx
NOTE 1: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, V
DDOD
, and V
DDOFB
.
NOTE 2: I
DDOx
denotes I
DDOA
, I
DDOB
, I
DDOC
, I
DDOD
, and I
DDOFB
.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDOX
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
Parameter
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
Input
D_SELA1:D_SELD1, PLL_SEL,
High Voltage FBDIV_SEL0, FBDIV_SEL1
REF_CLK
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
Input
Low Voltage D_SELA1, D_SELD1, PLL_SEL
REF_CLK
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
Input
FBDIV_SEL1
High Current
XTAL_SEL, PLL_SEL,
FBDIV_SEL0, OEA:OED
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
Input
FBDIV_SEL1
Low Current
XTAL_SEL, PLL_SEL,
FBDIV_SEL0, OEA:OED
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
-5
5
Test Conditions
Minimum
2
2
-0.3
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= 3.465V,
V
IN
= 0V
-5
-150
2.6
0.5
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
µA
µA
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OZL
I
OZH
Output Tristate Current High
NOTE 1: Outputs terminated with 50
Ω
to V
DDOx
/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
8761CY
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5
REV. C SEPTEMBER 7, 2004
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