IDT70V659S datasheet, PDF - EEWORLD Datasheet

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IDT70V659S: Description128K X 36 DUAL-PORT SRAM, 12 ns, PBGA256; Categorystorage; File Size196KB，23 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70V659S Overview

128K X 36 DUAL-PORT SRAM, 12 ns, PBGA256

IDT70V659S Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	256
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.45 V
Minimum supply/operating voltage	3.15 V
Rated supply voltage	3.3 V
maximum access time	12 ns
Processing package description	17 × 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID array, low PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	tin lead
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	36
organize	128K × 36
storage density	4.72E6 deg
operating mode	ASYNCHRONOUS
Number of digits	131072 words
Number of digits	128K
Memory IC type	dual-port static random access memory
serial parallel	parallel

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HIGH-SPEED 3.3V 128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

Features

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 10/12/15ns (max.)

– Industrial: 12/15ns (max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V659 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

PRELIMINARY

IDT70V659S

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 208-pin Plastic Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

1 L

0 L

CE1L

0 R

CE1R

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

128K x 36

MEMORY

ARRAY

I/O - I/O

35L

Di n_L

Di n_R

I/O - I/O

35R

A16 L

A0 L

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

16R

0 L

CE1L

R/WL

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

0 R

CE1R

R/WR

BUSY

SEM

INT

M/S

SEM

INT

TDI

TDO

JTAG

TMS

TCK

TRST

4869 drw 01

NOTES:

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

JUNE 2001

DSC-4869/3

IDT70V659S Related Products

	IDT70V659S	IDT70V659
Description	128K X 36 DUAL-PORT SRAM, 12 ns, PBGA256	128K X 36 DUAL-PORT SRAM, 12 ns, PBGA256
Number of functions	1	1
Number of terminals	256	256
Maximum operating temperature	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-40 Cel
Maximum supply/operating voltage	3.45 V	3.45 V
Minimum supply/operating voltage	3.15 V	3.15 V
Rated supply voltage	3.3 V	3.3 V
maximum access time	12 ns	12 ns
Processing package description	17 × 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256	17 × 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
state	ACTIVE	ACTIVE
Craftsmanship	CMOS	CMOS
packaging shape	SQUARE	SQUARE
Package Size	GRID array, low PROFILE	GRID array, low PROFILE
surface mount	Yes	Yes
Terminal form	BALL	BALL
Terminal spacing	1 mm	1 mm
terminal coating	tin lead	tin lead
Terminal location	BOTTOM	BOTTOM
Packaging Materials	Plastic/Epoxy	Plastic/Epoxy
Temperature level	INDUSTRIAL	INDUSTRIAL
memory width	36	36
organize	128K × 36	128K × 36
storage density	4.72E6 deg	4.72E6 deg
operating mode	ASYNCHRONOUS	ASYNCHRONOUS
Memory IC type	dual-port static random access memory	dual-port static random access memory
serial parallel	parallel	parallel
Number of digits	128K	128K

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