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IS61WV12816DBLS

Description
128K X 16 STANDARD SRAM, 12 ns, PBGA48
Categorystorage   
File Size202KB,21 Pages
ManufacturerISSI(Integrated Silicon Solution Inc.)
Websitehttp://www.issi.com/
Download Datasheet Parametric View All

IS61WV12816DBLS Overview

128K X 16 STANDARD SRAM, 12 ns, PBGA48

IS61WV12816DBLS Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals48
Maximum operating temperature125 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage2.4 V
Rated supply voltage3.3 V
maximum access time12 ns
Processing package description6 X 8 MM, LEAD FREE, MINI, BGA-48
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeGRID ARRAY, THIN PROFILE, FINE PITCH
surface mountYes
Terminal formBALL
Terminal spacing0.7500 mm
terminal coatingTIN SILVER COPPER
Terminal locationBOTTOM
Packaging MaterialsPLASTIC/EPOXY
Temperature levelAUTOMOTIVE
memory width16
organize128K X 16
storage density2.10E6 deg
operating modeASYNCHRONOUS
Number of digits131072 words
Number of digits128K
Memory IC typeSTANDARD SRAM
serial parallelPARALLEL
IS61WV12816DALL/DALS
IS61WV12816DBLL/DBLS
IS64WV12816DBLL/DBLS
128K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM
FEATURES
HIGH SPEED: (IS61/64WV12816DALL/DBLL)
• High-speed access time: 8, 10, 12, 20 ns
• Low Active Power: 135 mW (typical)
• Low Standby Power: 12
μW
(typical)
CMOS standby
LOW POWER: (IS61/64WV12816DALS/DBLS)
• High-speed access time: 25, 35 ns
• Low Active Power: 55 mW (typical)
• Low Standby Power: 12
μW
(typical)
CMOS standby
• Single power supply
— V
DD
1.65V to 2.2V (IS61WV12816DAxx)
— V
DD
2.4V to 3.6V (IS61/64WV12816DBxx)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
JULY 2011
DESCRIPTION
The
ISSI
IS61WV12816DAxx/DBxx and IS64WV12816DBxx
are high-speed, 2,097,152-bit static RAMs organized as
131,072 words by 16 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields high-performance and low power consumption de-
vices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV12816DAxx/DBxx and IS64WV12816DBxx are
packaged in the JEDEC standard 44-pin TSOP Type II and
48-pin Mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
06/21/2011
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