72 Mb (2M x 36 & 4M x 18)
7
QUADP (Burst of 4) Synchronous SRAMs
Q
.
I
May 2009
Features
•
2M
x 36 or
4M
x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Separate read and write ports with concurrent
read and write operations.
• Synchronous pipeline read with late write opera-
tion.
• Double data rate (DDR) interface for read and
write input ports.
• Fixed 4-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Two echo clocks (CQ and
CQ)
that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V V
DDQ
,
used with 0.75, 0.9V V
REF
.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The
72Mb IS61QDPB42M36
and
IS61QDPB44M18
are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed.
Refer to the
Timing Reference Diagram for Truth
Table
on page
8
for a description of the basic opera-
tions of these
QUADP (Burst of 4)
SRAMs.
Read and write addresses are registered on alter-
nating rising edges of the K clock. Reads and writes
are performed in double data rate. The following are
registered internally on the rising edge of the K
clock:
•
•
•
•
•
Read/write address
Read enable
Write enable
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3
• Byte writes for burst addresses 2 and 4
• Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle after the write address. The first
data-in burst is clocked one cycle later than the write
command signal, and the second burst is timed to
the following rising edge of the K clock. Two full
clock cycles are required to complete a write opera-
tion.
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
The following are registered on the rising edge of
the K clock:
Integrated Silicon Solution, Inc.
Rev.
A
05/14/09
1
72 Mb (2M x 36 & 4M x 18)
QUADP (Burst of 4) Synchronous SRAMs
x36 FBGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
Doff
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC/SA*
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
SA
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
2
BW
3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
NC
NC
7
BW
1
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
NC/SA*
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Note:
*The
following pins are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb.
QVLD pin (6P) is not supported.
x18 FBGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA*
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
SA
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
NC
NC
7
NC
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Note:
*The
following pins are reserved for higher densities: 2A for 144Mb.
QVLD pin (6P) is not supported.
2
Integrated Silicon Solution, Inc.
Rev.
A
05/14/09
72 Mb (2M x 36 & 4M x 18)
QUADP (Burst of 4) Synchronous SRAMs
Pin Description
Symbol
K, K
.
CQ, CQ
Doff
SA
SA
D0–D8
D9–D17
D18–D26
D27–D35
Q0–Q8
Q9–Q17
Q18–Q26
Q27–Q35
D0–D8
D9–D17
Q0–Q8
Q9–Q17
W
R
11A, 1A
1H
3A,
9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R,
7R,
8R, 9R
Output echo clock.
DLL disable when low.
2M
x 36 address inputs.
6B, 6A
Pin Number
Input clock.
Description
3A, 9A, 10A,
4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R,
4M
x 18 address inputs.
5R,
7R, 8R, 9R
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
10N, 9M, 9L, 9J, 10G, 9F, 10D, 9C, 9B
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
1C, 1D, 2E, 1G, 1J, 2K, 1M, 1N, 2P
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
9P, 9N, 10L, 9K, 9G, 10F, 9E, 9D, 10B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
1B, 2C, 1E, 1F, 2J, 1K, 1L, 2M, 1P
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
4A
8A
2M
x 36 data inputs.
2M
x 36 data outputs.
4M
x 18 data inputs.
4M
x 18 data outputs.
Write control, active low.
Read control, active low.
2M
x 36 byte write control, active low.
4M
x 18 byte write control, active low.
Input reference level.
Power supply.
Output power supply.
Ground.
Output driver impedance control.
IEEE 1149.1 test inputs (1.8V LVTTL lev-
els).
IEEE 1149.1 test output (1.8V LVTTL level).
BW
0,
BW
1,
BW
2,
BW
3
7B, 7A, 5A,5B
BW
0,
BW
1
V
REF
V
DD
V
DDQ
V
SS
ZQ
TMS, TDI, TCK
TDO
NC for x36
NC for x18
7B, 5A
2H, 10H
5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
6K, 5L, 6L, 7L, 4M, 5M, 6M, 7M, 8M, 4N, 8N
11H
10R, 11R, 2R
1R
2A, 10A, 6C,
6P, 6R
2A, 7A, 1B, 5B, 9B, 10B, 1C, 2C, 6C, 9C, 1D, 9D, 10D, 1E, 2E,
9E, 1F, 9F, 10F, 1G, 9G, 10G, 1J, 2J, 9J, 1K, 2K, 9K, 1L, 9L,
10L, 1M, 2M, 9M, 1N, 9N, 10N, 1P,
2P,
6P,
9P,
6R
Integrated Silicon Solution, Inc.
Rev.
A
05/14/09
3
72 Mb (2M x 36 & 4M x 18)
Q
QUADP (Burst of 4) Synchronous SRAMs
I
3
Block Diagram
D (Data-In)
36 (o r 18)
Data
Reg
72 (or 36 )
72 (or 36)
Wr ite Driver
Output Reg
72
(or 36)
144
(or 72)
Wr ite/Read Decode
Output Select
Address
Output Driver
19 (o r 20)
Add
Reg
19 (or 20 )
36 ( or 18)
Q (D ata- Out)
CQ, CQ
(Ech o Cloc k Out)
R
W
BW
x
K
K
C
Doff
4 (or 2)
Control
Logic
2M
x 36
(4M x 18)
Memory
Array
S ense Am ps
72
(or 36)
Cloc k
Gen
Select Output Control
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R in active
low state at the rising edge of the K clock. R can be activated every other cycle because two full cycles are
required to complete the burst of four in DDR mode.
A set of free-running echo clocks, CQ and CQ, are
produced internally with timings
identical to the data-outs. The echo clocks can be used as data capture
clocks by the receiver device.
The
data corresponding to the first address is clocked
2.5
cycles later by the rising edge of the
K
clock.
The data corresponding to the second burst is clocked
3
cycles later by the following rising edge of the K
clock. The third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is
clocked by the subsequent rising edge of the K clock.
A NOP operation (R is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every other rising edge of the K clock whenever W is low. The write
address is provided simultaneously. Again, the write always occurs in bursts of four.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the
second write burst address follows next, registered by the rising edge of K. The third data-in is clocked by the
subsequent rising edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the
K clock.
4
Integrated Silicon Solution, Inc.
Rev.
A
05/14/09
72 Mb (2M x 36 & 4M x 18)
Q
QUADP (Burst of 4) Synchronous SRAMs
I
3
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into
the array on the third write cycle. A read cycle to the last two write addresses produces data from the write
buffers. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written
(see
X18/X36 Write Truth Tables
on pages
10
- 11
and
Timing Reference Diagram for Truth Table
on page
8).
Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics
on page 16. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to V
DDQ
to obtain a minimum impedance setting. ZQ must never
be connected to V
SS
.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within
2048
clock cycles.
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all
pending read and write transactions are always completed prior to deselecting the corresponding port.
Integrated Silicon Solution, Inc.
Rev.
A
05/14/09
5
京公网安备 11010802033920号
EEWORLD
