PRELIMINARY
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-
LVDS/LVCMOS FREQUENCY SYNTHESIZER
ICS8440258-46
G
ENERAL
D
ESCRIPTION
The ICS8440258-46 is an 8 output synthesizer
optimized to generate Ethernet clocks and a
HiPerClockS™
member of the HiPerClock S ™ family of high
performance clock solutions from IDT. Using a
25MHz, 18pF parallel resonant crystal, the device
will generate both 125MHz and 25MHz clocks with mixed
LVDS and LVCMOS/LVTTL output logic. The ICS8440258-46
uses IDT’s 3
rd
generations low phase noise VCO technology
and can achieve <1ps typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS8440258-46 is packaged
in a small, 5mm x 5mm VFQFN package.
F
EATURES
•
Four differential LVDS outputs at 125MHz
Two LVCMOS/LVTTL single-ended outputs at 125MHz
Two LVCMOS/LVTTL single-ended outputs at 25MHz
•
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
•
VCO range: 490MHz - 680MHz
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.34ps (typical)
•
Full 2.5V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS6)
packages
nXTAL_SEL
XTAL_OUT
nPLL_SEL
REF_CLK
XTAL_IN
IC
S
P
IN
A
SSIGNMENT
Q0
nQ0
GND
Q1
nQ1
V
DD
1
2
3
4
5
6
7
8
V
DDA
V
DD
32 31 30 29 28 27 26 25
24
23
nc
nc
nc
GND
Q7
V
DDO
2
Q6
GND
ICS8440258-46
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
9 10 11 12 13 14 15 16
V
DDO
1
GND
GND
V
DD
Q3
Q4
nQ3
Q5
MR
22
21
20
19
18
17
B
LOCK
D
IAGRAM
MR
Pulldown
Q0
nPLL_SEL
Pulldown
Q2
nQ2
nQ0
Q1
nQ1
25MHz
XTAL_IN
Q2
OSC
XTAL_OUT
REF_CLK
Pulldown
0
Phase
Detector
1
VCO
490-680MHz
1
÷5
0
nQ2
Q3
nQ3
Q4
nXTAL_SEL
Pulldown
÷25
Q5
Q6
Q7
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
1
ICS8440258AK-46 REV B JANUARY 15, 2008
ICS8440258-46
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 12, 16,
17, 21
4, 5
6, 11, 27
7, 8
9, 10
13, 15,
18, 20
14
19
22, 23, 24
25
Name
Q0, nQ0
GND
Q1, nQ1
V
DD
Q2, nQ2
Q3, nQ3
Q4, Q5,
Q6, Q7
V
DDO1
V
DDO2
nc
V
DDA
Type
Output
Power
Output
Power
Output
Output
Output
Power
Power
Unused
Power
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Core supply pin.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power output supply pin for Q4 and Q5 LVCMOS outputs.
Power output supply pin for Q6 and Q7 LVCMOS outputs.
No connect.
Analog supply pin.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency =
26
nPLL_SEL
Input
Pulldown
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
28
MR
Input
Pulldown reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
29
REF_CLK
Input
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
Selects between the crystal or REF_CLK inputs as the PLL reference
30
nXTAL_SEL
Input
Pulldown source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
31,
XTAL_OUT,
Crystal oscillator interface. XTAL_OUT is the output.
Input
32
XTAL_IN
XTAL_IN is the input.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
8
51
22
Maximum
Units
pF
pF
kΩ
Ω
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
2
ICS8440258AK-46 REV B JANUARY 15, 2008
ICS8440258-46
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
10mA
15mA
-40°C to +85°C
-65°C to 150°C
37°C/W (0 mps)
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO1
= V
DDO2
= 2.5V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD,
I
DDO1,
I
DDO2
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.13
2.375
Typical
2.5
2.5
2.5
170
13
Maximum
2.625
V
DD
2.625
Units
V
V
V
mA
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO1
= V
DDO2
= 2.5V ± 5%,T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
V
OH
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
MR, REF_CLK,
nPLL_SEL, nXTAL_SEL
MR, REF_CLK,
nPLL_SEL, nXTAL_SEL
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-5
Test Conditions
Minimum Typical
1.7
-0.3
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
µA
Output
High Voltage; Q4:Q7
1.8
V
DDO1,
V
DDO1
= 2.625V±5%
NOTE 1
Output
Low Voltage; Q4:Q7
V
OL
V
DDO1,
V
DDO1
= 2.625V±5%
NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDOX
/2. See Parameter Measurement Information,
Output Load Test Circuit diagram.
V
0.5
V
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
3
ICS8440258AK-46 REV B JANUARY 15, 2008
ICS8440258-46
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
3C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO1
= V
DDO2
= 2.5V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
390
50
1.25
50
Maximum
Units
mV
mV
V
mV
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
Test Conditions
Minimum
Typical
25
50
7
1
Maximum
Units
MHz
Ω
pF
mW
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO1
= V
DDO2
= 2.5V ± 5%,T
A
= 0°C
TO
70°C
Symbol
f
OUT
Parameter
Q0:3/nQ0:3
Output Frequency
Output Skew;
NOTE 1, 2
RMS Phase Jitter
(Random); NOTE 3
Output
Rise/Fall Time
Output Duty Cycle
Q4, Q5
Q6, Q7
Q0:3/nQ0:3
Q4:Q7
Q0:3/nQ0:3
Q4, Q5
Q0:3/nQ0:3
Q4:Q7
Q0:3/nQ0:3
125MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
20% to 80%
20% to 80%
Test Conditions
Minimum
Typical
125
125
25
50
50
0.34
0.37
480
1.4
50
54
Maximum
Units
MHz
MHz
MH z
ps
ps
ps
ps
ps
ns
%
%
t
sk(o)
t
jit(Ø)
t
R
/ t
F
odc
Q4:Q7
46
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
4
ICS8440258AK-46 REV B JANUARY 15, 2008
ICS8440258-46
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
(
LVCMOS
)
-10
-20
-30
-40
-50
➤
Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.37ps (typical)
0
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
Raw Phase Noise Data
➤
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
10
100
➤
1k
10k
Phase Noise Result by adding
Ethernet Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
(
LVDS
)
-10
-20
-30
-40
-50
➤
Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.34ps (typical)
0
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-180
-190
-200
10
100
1k
10k
-170
Raw Phase Noise Data
O
FFSET
F
REQUENCY
(H
Z
)
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
➤
➤
Phase Noise Result by adding
Ethernet Filter to raw data
100k
1M
10M
100M
5
ICS8440258AK-46 REV B JANUARY 15, 2008
京公网安备 11010802033920号
EEWORLD
