HM5212165FLTD-75/A60/B60
HM5212805FLTD-75/A60/B60
Description
The HM5212165F L is a 128-Mbit S DRA M orga nized as 2097152-w ord
×
16-bit
×
4-ba nk. The
HM5212805FL is a 128-Mbit SDRAM organized as 4194304-word
×
8-bit
×
4-bank. All inputs and outputs are
referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
•
•
•
•
•
•
•
•
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed
RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
•
Programmable
CAS
latency: 2/3
•
Byte control by DQM : DQM (HM5212805FL)
: DQMU/DQML (HM5212165FL)
•
Refresh cycles: 4096 refresh cycles/64 ms
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
EO
128M LVTTL interface SDRAM
133 MHz/100 MHz
2-Mword
×
16-bit
×
4-bank/4-Mword
×
8-bit
×
4-bank
PC/133, PC/100 SDRAM
E0180H10 (Ver. 1.0)
Jul. 17, 2001
L
Pr
uc
od
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
•
2 variations of refresh
Auto refresh
Self refresh
•
Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No.
HM5212165FLTD-75*
1
HM5212165FLTD-A60
HM5212165FLTD-B60*
2
HM5212805FLTD-75*
1
HM5212805FLTD-A60
HM5212805FLTD-B60*
2
Notes: 1. 100 MHz operation at
CAS
latency = 2.
2. 66 MHz operation at
CAS
latency = 2.
2
EO
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
Frequency
CAS
latency
3
2/3
3
3
2/3
3
Package
400-mil 54-pin plastic TSOP II (TTP-54DA)
L
Data Sheet E0180H10
Pr
uc
od
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Pin Arrangement
(HM5212165F)
Pin Description
Pin name
A0 to A13
Function
Address input
Row address
Column address
DQ0 to DQ15
CS
RAS
CAS
WE
Data-input/output
Chip select
Row address strobe command
Column address strobe command
Write enable
A0 to A11
A0 to A8
EO
54-pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
DQML
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
Bank select address A12/A13 (BS) V
CC
V
SS
L
(Top view)
Data Sheet E0180H10
3
Pr
uc
od
Pin name
Function
DQMU/DQML
Input/output mask
CLK
Clock input
CKE
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
V
CC
Q
V
SS
Q
NC
Ground for DQ circuit
No connection
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Pin Arrangement
(HM5212805F)
Pin Description
Pin name
A0 to A13
Function
Address input
Row address
Column address
DQ0 to DQ7
CS
RAS
CAS
WE
Data-input/output
Chip select
Row address strobe command
Column address strobe command
Write enable
A0 to A11
A0 to A9
4
EO
54-pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
CC
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
Bank select address A12/A13 (BS) V
CC
V
SS
L
(Top view)
Data Sheet E0180H10
Pr
uc
od
Pin name
DQM
Function
Input/output mask
CLK
Clock input
CKE
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
V
CC
Q
V
SS
Q
NC
Ground for DQ circuit
No connection
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Block Diagram
(HM5212165F)
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Memory array
Bank0
Memory array
Column decoder
Bank1
Memory array
Column decoder
Bank2
4096 row
×
512 column
×
8 bit
Sense amplifier & I/O bus
Column decoder
Column decoder
Control logic &
timing generator
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Column decoder
Column decoder
Column decoder
Column decoder
EO
Column address
counter
Row decoder
4096 row
×
512 column
×
8 bit
Memory array
Bank0
4096 row
×
512 column
×
8 bit
Row decoder
Column address
counter
A0 to A13
Upper pellet
A0 to A8
Column address
buffer
A0 to A13
Row address
buffer
Refresh
counter
Row decoder
Row decoder
Row decoder
Memory array
Bank3
4096 row
×
512 column
×
8 bit
L
Input buffer
DQ8 to DQ15
DQ0 to DQ7
Input buffer
Bank1
4096 row
×
512 column
×
8 bit
Data Sheet E0180H10
5
Pr
Output buffer
Output buffer
Memory array
Memory array
Bank2
4096 row
×
512 column
×
8 bit
4096 row
×
512 column
×
8 bit
Row decoder
Row decoder
Column address
buffer
Row address
buffer
Refresh
counter
CLK
CKE
CS
RAS
CAS
WE
DQMU
/DQML
uc
od
Memory array
Bank3
4096 row
×
512 column
×
8 bit
Row decoder
t
Lower pellet