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HD74HC161P

Description
Synchronous Decade Counter (Direct Clear)
Categorylogic    logic   
File Size154KB,15 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Environmental Compliance
Download Datasheet Parametric View All

HD74HC161P Overview

Synchronous Decade Counter (Direct Clear)

HD74HC161P Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?conform to
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
ECCN codeEAR99
Counting directionUP
seriesHC/UH
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.2 mm
Load capacitance (CL)50 pF
Load/preset inputYES
Logic integrated circuit typeBINARY COUNTER
Maximum Frequency@Nom-Su20000000 Hz
MaximumI(ol)0.004 A
Operating modeSYNCHRONOUS
Humidity sensitivity level1
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2/6 V
propagation delay (tpd)200 ns
Certification statusNot Qualified
Maximum seat height5.06 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)4.5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
Base Number Matches1
HD74HC160/HD74HC161/HD74HC162/
HD74HC163
Synchronous Decade Counter (Direct Clear)
Synchronous 4-bit Binary Counter (Direct Clear)
Synchronous Decade Counter (Synchronous Clear)
Synchronous 4-bit Binary Counter (Synchronous Clear)
REJ03D0579-0200
(Previous ADE-205-455)
Rev.2.00
Oct 11, 2005
Description
The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the HD74HC163 are 4 bit
binary counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock
input waveform.
These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to the rising edge of
clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs is loaded into the counter
on the rising edge of clock. If the load input is taken high before the positive edge of clock the count operation will be
unaffected.
All of these counters may be cleared by the utilizing clear input. The clear function on the HD74HC162 and
HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive edge of clock
while the clear input is held low.
The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the counter is
cleared immediately regardless of the clock.
Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy cascading of
counters. Both enable inputs must be high to count. The Enable T input also enables the Ripple Carry output. When
enabled, the Ripple Carry outputs a positive pulse when the counter overflows. This pulse is approximately equal in
duration to the high level portion of the Q
A
outputs. The Ripple Carry output is fed to successive cascaded stages to
facilitate easy implementation of N-bit counters.
Features
High Speed Operation: t
pd
(Clock to Q) = 18 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
Rev.2.00, Oct 11, 2005 page 1 of 14

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