HB52R329E22-F
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Description
Features
256 MB Registered SDRAM DIMM
32-Mword
×
72-bit, 100 MHz Memory Bus, 2-Bank Module
(36 pcs of 16 M
×
4 Components)
PC100 SDRAM
E0112H10 (1st edition)
(Previous ADE-203-1046A (Z))
Feb. 28, 2001
The HB 52R 329E22 belongs to 8-byte DI MM (D ual In- line Memory Module) fa mily, and has bee n deve loped
as an optimiz ed main memory solution for 8-byte proc essor applica tions. The HB 52R 329E22 is a 16M
×
72
×
2-ba nk S ynchronous Dyna mic R AM Module, mounted 36 piec es of 64-Mbit S DRA M (H M5264405F TB )
sea led in TC P pac kage and 1 piec e of P LL cloc k drive r (2510) , 3 piec es re giste r drive r (162835) , 1 piec e of
inver te r and 1 piec e of ser ia l EEP RO M (2- kbit EEP RO M) for P rese nce De te ct (P D). An outline of the
HB 52R 329E22 is 168-pin socke t type pac kage (dua l lea d out). The ref ore, the HB 52R 329E22 make s high
density mounting possible without surf ace mount tec hnology. The HB 52R 329E22 provide s common data
inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be
electrical defects.
•
Fully compatible with : JEDEC standard outline registered 8-byte DIMM
: Intel PCB Reference design (Rev. 1.2)
•
168-pin socket type package (dual lead out)
Outline: 133.37 mm (length)
×
38.10 mm (Height)
×
4.80 mm (Thickness)
Lead pitch: 1.27 mm
•
3.3 V power supply
•
Clock frequency: 100 MHz (max)
•
LVTTL interface
•
Data bus width:
×
72 ECC
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length: 1/2/4/8/full page
•
2 variations of burst sequence
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HB52R329E22-F
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
•
Programmable
CE
latency : 3/4 (HB52R329E22-A6F)
: 4 (HB52R329E22-B6F)
•
Byte control by DQMB
•
Refresh cycles: 4096 refresh cycles/64 ms
•
2 variations of refresh
Auto refresh
Self refresh
•
Full page burst length capability
Sequential burst
Burst stop capability
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Ordering Information
Type No.
HB52R329E22-A6F
HB52R329E22-B6F
100 MHz
100 MHz
2
L
Frequency
CE
latency
3/4
4
Package
168-pin dual lead out socket type
Contact pad
Gold
Data Sheet No. E0112H10
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HB52R329E22-F
Pin Description
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Pin name
A0 to A11
A13/A12
DQ0 to DQ63
CB0 to CB7
S0
to
S3
RE
CE
W
DQMB0 to DQMB7
CK0 to CK3
CKE0
WP
REGE*
1
SDA
SCL
SA0 to SA2
V
CC
V
SS
NC
Note:
Function
Address input
Row address
Column address
Bank select address
Data input/output
Check bit (Data input/output)
Chip select input
Row enable (RAS) input
Column enable (CAS) input
Write enable input
A0 to A11
A0 to A9
BA0/BA1
1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high state
(“registerd” mode).
L
Byte data mask
Clock input
Clock enable input
Data Sheet No. E0112H10
5
o
Pr
Write protect for serial PD
Register enable
Data input/output for serial PD
Clock input for serial PD
Serial address input
Primary positive power supply
Ground
No connection
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