4-STAGE PRESETTABLE
RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and di-
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The
SN54/74LS197 contains divide-by-two and divide-by-eight sections which
can be combined to form a modulo-16 binary counter. Low Power Schottky
technology is used to achieve typical count rates of 70 MHz and power dis-
sipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Par-
allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits
usable as programmable counters. The circuits can also be used as 4-bit
latches, loading data from the Parallel Data inputs when PL is LOW and stor-
ing the data when PL is HIGH.
SN54/74LS196
SN54/74LS197
4-STAGE PRESETTABLE
RIPPLE COUNTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
14
1
•
•
•
•
•
•
•
Low Power Consumption — Typically 80 mW
High Counting Rates — Typically 70 MHz
Choice of Counting Modes — BCD, Bi-Quinary, Binary
Asynchronous Presettable
Asynchronous Master Reset
Easy Multistage Cascading
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
14
MR
13
Q3
12
P3
11
P1
10
Q1
9
CP0
8
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
1
PL
2
Q2
3
P2
4
P0
5
Q0
6
CP1
7
GND
PIN NAMES
LOADING
(Note a)
HIGH
LOW
1.5 U.L.
1.75 U.L.
0.8 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
8
6
LOGIC SYMBOL
1
PL
4 10 3 11
P0 P1 P2 P3
CP0
CP1 (LS196)
CP1 (LS197)
MR
PL
P0–P3
Q0–Q3
Clock (Active LOW Going Edge)
Input to Divide-by-Two Section
Clock (Active LOW Going Edge)
Input to Divide-by-Five Section
Clock (Active LOW Going Edge)
Input to Divide-by-Eight Section
Master Reset (Active LOW) Input
Parallel Load (Active LOW) Input
Data Inputs
Outputs (Notes b, c)
1.0 U.L.
2.0 U.L.
1.0 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
CP0
CP1
MR
13
Q0 Q1 Q2 Q3
5
9 2 12
VCC = PIN 14
GND = PIN 7
NOTES:
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
c. In addition to loading shown, Q0 can also drive CP1.
FAST AND LS TTL DATA
5-372
SN54/74LS196
•
SN54/74LS197
LOGIC DIAGRAM
MR
PL
13
P0
4
P1
10
P2
3
P3
11
1
8
J SD Q
J SD Q
J SD Q
J SD Q
CP0
K CD Q
6
K CD Q
K CD Q
K CD Q
CP1
Q0
5
9
2
12
Q1
Q2
Q3
LS196
MR
PL
13
P0
4
P1
10
P2
3
P3
11
1
8
J SD Q
J SD Q
J SD Q
J SD Q
CP0
K CD Q
6
K CD Q
K CD Q
K CD Q
CP1
Q0
5
9
2
12
Q1
Q2
Q3
LS197
VCC = PIN 14
GND = PIN 7
= PIN NUMBERS
FAST AND LS TTL DATA
5-373
SN54/74LS196
•
SN54/74LS197
FUNCTIONAL DESCRIPTION
The LS196 and LS197 are asynchronously presettable de-
cade and binary ripple counters. The LS196 Decade Counter
is partitioned into divide-by-two and divide-by-five sections
while the LS197 is partitioned into divide-by-two and divide-
by-eight sections, with all sections having a separate Clock in-
put. In the counting modes, state changes are initiated by the
HIGH to LOW transition of the clock signals. State changes of
the Q outputs, however, do not occur simultaneously because
of the internal ripple delays. When using external logic to de-
code the Q outputs, designers should bear in mind that the un-
equal delays can lead to decoding spikes and thus a decoded
signal should not be used as a clock or strobe. The CP0 input
serves the Q0 flip-flop in both circuit types while the CP1 input
serves the divide-by-five or divide-by-eight section. The Q0
output is designed and specified to drive the rated fan-out plus
the CP1 input. With the input frequency connected to CP0 and
Q0 driving CP1, the LS197 forms a straightforward module-16
counter, with Q0 the least significant output and Q3 the most
significant output.
The LS196 Decade Counter can be connected up to oper-
ate in two different count sequences, as indicated in the tables
of Figure 2. With the input frequency connected to CP0 and
with Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1)
sequence. With the input frequency connected to CP1 and Q3
driving CP0, Q0 becomes the low frequency output and has a
50% duty cycle waveform. Note that the maximum counting
rate is reduced in the latter (bi-quinary) configuration because
of the interstage gating delay within the divide-by-five section.
The LS196 and LS197 have an asynchronous active LOW
Master Reset input (MR) which overrides all other inputs and
forces all outputs LOW. The counters are also asynchronously
presettable. A LOW on the Parallel Load input (PL) overrides
the clock inputs and loads the data from Parallel Data (P0 – P3)
inputs into the flip-flops. While PL is LOW, the counters act as
transparent latches and any change in the Pn inputs will be re-
flected in the outputs.
Figure 2. LS196 COUNT SEQUENCES
DECADE (NOTE 1)
COUNT
0
1
2
3
4
5
6
7
8
9
Q3
L
L
L
L
L
L
L
L
H
H
Q2
L
L
L
L
H
H
H
H
L
L
Q1
L
L
H
H
L
L
H
H
L
L
Q0
L
H
L
H
L
H
L
H
L
H
COUNT
0
1
2
3
4
5
6
7
8
9
Q0
L
L
L
L
L
H
H
H
H
H
BI-QUINARY (NOTE 2)
Q3
L
L
L
L
H
L
L
L
L
H
Q2
L
L
H
H
L
L
L
H
H
L
Q1
L
H
L
H
L
L
H
L
H
L
NOTES:
1. Signal applied to CP0, Q0 connected to CP1.
2. Signal applied to CP1, Q3 connected to CP0.
MODE SELECT TABLE
INPUTS
RESPONSE
MR
L
H
H
PL
X
L
H
CP
X
X
Reset (Clear)
Parallel Load
Count
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= HIGH to Low Clock Transition
FAST AND LS TTL DATA
5-374
SN54/74LS196
•
SN54/74LS197
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
Data, PL
MR, CP0 (LS196)
MR, CP0, CP1 (LS197)
CP1 (LS196)
Data, PL
MR, CP0 (LS196)
MR, CP0, CP1 (LS197)
CP1 (LS196)
Input LOW Current
Data, PL
MR
CP0
CP1 (LS196)
CP1 (LS197)
Short Circuit Current (Note 1)
Power Supply Current
– 20
0.35
0.5
20
40
40
80
0.1
0.2
0.2
0.4
– 0.4
– 0.8
– 2.4
– 2.8
– 1.3
– 100
27
V
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
µA
VCC = MAX, VIN = 2.7 V
IIH
mA
VCC = MAX, VIN = 7.0 V
IIL
mA
VCC = MAX, VIN = 0.4 V
IOS
ICC
mA
mA
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-375
SN54/74LS196
•
SN54/74LS197
AC CHARACTERISTICS
(TA = 25°C)
Limits
LS196
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
CP0 Input to
Q0 Output
CP1 Input to
Q1 Output
CP1 Input to
Q2 Output
CP1 Input to
Q3 Output
Data to Output
PL Input to
Any Output
MR Input to Any Output
Min
30
Typ
40
8.0
13
16
22
38
41
12
30
20
29
27
30
34
15
20
24
33
57
62
18
45
30
44
41
45
51
Max
Min
30
LS197
Typ
40
8.0
14
12
23
34
42
55
63
18
29
26
30
34
15
21
19
35
51
63
78
95
27
44
39
45
51
Max
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS
(TA = 25°C)
Limits
LS196
Symbol
tW
tW
tW
tW
ts
ts
th
th
trec
Parameter
CP0 Pulse Width
CP1 Pulse Width
PL Pulse Width
MR Pulse Width
Data Input Setup Time — HIGH
Data Input Setup Time — LOW
Data Hold Time — HIGH
Data Hold Time — LOW
Recovery Time
Min
20
30
20
15
10
15
10
10
30
Typ
Max
Min
20
30
20
15
10
15
10
10
30
LS197
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from HIGH to LOW in order to recognize and transfer
LOW Data to the Q outputs.
FAST AND LS TTL DATA
5-376
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