5821
AND
5822
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A merged combination of bipolar and MOS technology gives
these devices an interface flexibility beyond the reach of standard
logic buffers and power driver arrays. The UCN5821A,
UCN5821LW, UCN5822A, and UCN5822LW each have an
eight-bit CMOS shift register and CMOS control circuitry, eight
CMOS data latches, and eight bipolar current-sinking Darlington
output drivers. The UCN5821A/LW and UCN5822A/LW are
identical except for rated output voltage.
BiMOS II devices have much higher data-input rates than the
original BiMOS circuits. With a 5 V logic supply, they will
typically operate at better than 5 MHz. With a 12 V supply,
significantly higher speeds are obtained. The CMOS inputs are
compatible with standard CMOS and NMOS logic levels. TTL
circuits may require the use of appropriate pull-up resistors. By
using the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.
The UCN5821/22A are furnished in a standard 16-pin plastic
DIP; the UCN5821/22LW are in a 16-lead wide-body SOIC for
surface-mount applications. The UCN5821A is also available for
operation from -40°C to +85°C. To order, change the prefix from
‘UCN’ to ‘UCQ’.
Data Sheet
26185.12E
CLOCK
SERIAL
DATA IN
LOGIC
GROUND
LOGIC
SUPPLY
SERIAL
DATA OUT
STROBE
OUTPUT
ENABLE
POWER
GROUND
1
2
3
4
5
6
7
8
CLK
16
15
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
SHIFT REGISTER
14
LATCHES
V
DD
13
12
11
10
9
ST
OE
SUB
Dwg. PP-026A
Note the DIP package and the SOIC package are
electrically identical and share common terminal
number assignments.
ABSOLUTE MAXIMUM RATINGS
at 25
°
C Free-Air Temperature
Output Voltage, V
OUT
UCN5821A & UCN5821LW .....
50 V
UCN5822A & UCN5822LW .....
80 V
Logic Supply Voltage, V
DD
.............
15 V
Input Voltage Range,
V
IN
..................
-0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
I
OUT
.....................................
500 mA
Package Power Dissipation, P
D
Package Code ‘A’ ..................
2.1 W
Package Code ‘LW’ ...............
1.5 W
Operating Temperature Range,
T
A
............................ -20
°
C to +85
°
C
Storage Temperature Range,
T
S
.......................... -55
°
C to +150
°
C
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
FEATURES
I
To 3.3 MHz Data Input Rate
I
CMOS, NMOS, TTL Compatible
I
Internal Pull-Down Resistors
I
Low-Power CMOS Logic & Latches
I
High-Voltage Current-Sink Outputs
I
Automotive Capable
Always order by complete part number, e.g.,
UCN5821A
.
www.allegromicro.com
5821
AND
5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
V
DD
CLOCK
SERIAL
DATA IN
LOGIC
GROUND
1
FUNCTIONAL BLOCK DIAGRAM
V
DD
4
LOGIC
SUPPLY
SERIAL
DATA OUT
STROBE
OUTPUT ENABLE
(ACTIVE LOW)
2
SERIAL-PARALLEL SHIFT REGISTER
5
3
LATCHES
6
IN
7
STROBE &
OUTPUT
ENABLE
16
15
14
13
12
11
10
9
MOS
BIPOLAR
8
POWER
GROUND
Dwg. FP-013A
SUB
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
Dwg. EP-010-3
NOTE — There is an indeterminate resistance between logic ground and power
ground. For proper operation, these terminals must be externally connected
together.
VDD
CLOCK &
SERIAL
DATA IN
IN
Number of Outputs ON
(I
OUT
= 200 mA
V
DD
= 12 V)
8
7
6
5
4
3
2
1
UCN5821A Max. Allowable Duty Cycle
at Ambient Temperature of
25
°
C
40
°
C
50
°
C
60
°
C
70
°
C
90%
100%
100%
100%
100%
100%
100%
100%
79%
90%
100%
100%
100%
100%
100%
100%
72%
82%
96%
100%
100%
100%
100%
100%
65%
74%
86%
100%
100%
100%
100%
100%
57%
65%
76%
91%
100%
100%
100%
100%
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
OUT
Number of Outputs ON
(I
OUT
= 200 mA
V
DD
= 12 V)
8
7
6
5
4
3
2
1
UCN5821LW Max. Allowable Duty Cycle
at Ambient Temperature of
25
°
C
40
°
C
50
°
C
60
°
C
70
°
C
67%
77%
90%
100%
100%
100%
100%
100%
59%
68%
79%
95%
100%
100%
100%
100%
54%
62%
72%
86%
100%
100%
100%
100%
49%
56%
65%
78%
98%
100%
100%
100%
43%
49%
57%
68%
86%
100%
100%
100%
7.2K
3K
SUB
Dwg. No. A-14,314
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000, Allegro MicroSystems, Inc.
5821
AND
5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
DD
= 5 V, (unless otherwise specified).
Limits
Characteristic
Output Leakage
Current
Symbol
I
CEX
Test Conditions
UCN5821A/LW, V
OUT
= 50 V
UCN5822A/LW, V
OUT
= 80 V
UCN5821A/LW, V
OUT
= 50 V, T
A
= +70°C
UCN5822A/LW, V
OUT
= 80 V, T
A
= +70°C
Collector-Emitter
Saturation Voltage
V
CE(SAT)
I
OUT
= 100 mA
I
OUT
= 200 mA
I
OUT
= 350 mA, V
DD
= 7.0 V
Input Voltage
V
IN(0)
V
IN(1)
V
DD
= 12 V
V
DD
= 5.0 V
Input Resistance
r
IN
V
DD
= 12 V
V
DD
= 5.0 V
Supply Current
I
DD(ON)
One Driver ON, V
DD
= 12 V
One Driver ON, V
DD
= 10 V
One Driver ON, V
DD
= 5.0 V
I
DD(OFF)
V
DD
= 5.0 V, All Drivers OFF, All Inputs = 0 V
V
DD
= 12 V, All Drivers OFF, All Inputs = 0 V
Min.
—
—
—
—
—
—
—
—
10.5
3.5
50
50
—
—
—
—
—
Max.
50
50
100
100
1.1
1.3
1.6
0.8
—
—
—
—
4.5
3.9
2.4
1.6
2.9
Units
µA
µA
µA
µA
V
V
V
V
V
V
kΩ
kΩ
mA
mA
mA
mA
mA
www.allegromicro.com
5821
AND
5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
Serial Data present at the input is
transferred to the shift register on the
logic “0” to logic “1” transition of the
CLOCK input pulse. On succeeding
CLOCK pulses, the registers shift data
information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge
of the CLOCK input waveform.
G
CLOCK
A
B
DATA IN
E
C
STROBE
F
D
OUTPUT
ENABLE
OUT
N
Dwg. No. A-12,627
TIMING CONDITIONS
(V
DD
= 5.0 V, T
A
= +25
°
C, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................
75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) ...........................................................................
75 ns
C.
Minimum Data Pulse Width ..............................................................
150 ns
D.
Minimum Clock Pulse Width ............................................................
150 ns
E.
F.
Minimum Time Between Clock Activation and Strobe .......................
30 ns
Minimum Strobe Pulse Width ...........................................................
100 ns
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel con-
version). The latches will continue to
accept new data as long as the STROBE
is held high. Applications where the
latches are bypassed (STROBE tied high)
will require that the ENABLE input be
high during serial data entry.
When the ENABLE input is high, all
of the output buffers are disabled (OFF)
without affecting the information stored
in the latches or shift register. With the
ENABLE input low, the outputs are
controlled by the state of the latches.
G.
Typical Time Between Strobe Activation and
Output Transition ..........................................................................
1.0
µ
s
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I
1
I
2
I
3
.............. I
8
H
L
X
H
L
R
1
R
2
.............. R
7
R
1
R
2
.............. R
7
X
X
.............. X
Serial
Data Strobe
Output Input
R
7
R
7
R
8
X
P
8
L
H
R
1
R
2
R
3
.............. R
8
P
1
P
2
P
3
.............. P
8
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
X
X
.............. X
L
H
P
1
P
2
P
3
..............
H H H ..............
P
8
H
Latch Contents
I
1
I
2
I
3
.............. I
8
Output
Enable
Output Contents
I
1
I
2
I
3
..............
I
8
R
1
R
2
R
3
.............. R
8
X
P
1
P
2
P
3
.............. P
8
P = Present State
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5821
AND
5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5821A and UCN5822A
Dimensions in Inches
(controlling dimensions)
16
9
0.014
0.008
0.430
0.280
0.240
MAX
0.300
BSC
1
0.070
0.045
0.100
0.775
0.735
BSC
8
0.005
MIN
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-16A in
Dimensions in Millimeters
(for reference only)
16
9
0.355
0.204
10.92
7.11
6.10
MAX
7.62
BSC
1
1.77
1.15
2.54
19.68
18.67
BSC
8
0.13
MIN
5.33
MAX
0.39
MIN
3.81
2.93
0.558
0.356
Dwg. MA-001-16A mm
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
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