5962H9652301QCA datasheet, PDF

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5962H9652301QCA: DescriptionAND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14; Categorylogic logic; File Size160KB，15 Pages; ManufacturerCobham PLC

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5962H9652301QCA Overview

AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

5962H9652301QCA Parametric

Parameter Name	Attribute value
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
ECCN code	3A001.A.1.A
series	ACT
JESD-30 code	R-XDIP-T14
JESD-609 code	e0
length	19.43 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND GATE
MaximumI(ol)	0.008 A
Number of functions	3
Number of entries	3
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Prop。Delay @ Nom-Sup	13 ns
propagation delay (tpd)	13 ns
Certification status	Qualified
Schmitt trigger	NO
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
total dose	1M Rad(Si) V
width	7.62 mm
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Changes in accordance with NOR 5962-R080-97. – JAK

Add limit for linear energy threshold (LET) with no latch-up in section 1.5.

Update the boilerplate to the requirements of MIL-PRF-38535. Editorial

changes throughout. – TVN

Update boilerplate paragraphs and radiation paragraphs 4.4.4.1 – 4.4.4.4 to

the current MIL-PRF-38535 requirements. - LTG

To correct switching waveforms input/output test limits to figure 4. Add test

equivalent circuits and footnote 4 to figure 4. Delete class M requirements

throughout.-- MAA

DATE (YR-MO-DA)

96-11-25

APPROVED

Monica L. Poelking

05-06-28

Thomas M. Hess

12-03-22

Thomas M. Hess

12-11-19

Thomas M. Hess

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Thanh V. Nguyen

CHECKED BY

Thanh V. Nguyen

APPROVED BY

Monica L. Poelking

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

DSCC FORM 2233

APR 97

DRAWING APPROVAL DATE

96-06-11

REVISION LEVEL

STANDARD

MICROCIRCUIT

DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

http://www.landandmaritime.dla.mil

MICROCIRCUIT, DIGITAL, RADIATION

HARDENED, ADVANCED CMOS, TRIPLE 3-INPUT

AND GATE, TTL COMPATIBLE INPUTS,

MONOLITHIC SILICON

SIZE

CAGE CODE

67268

SHEET

1 OF 14

5962-96523

5962-E079-13

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table. The truth table shall be as specified on figure 2.

3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.

3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4.

3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document

revision level control and shall be made available to the preparing and acquiring activity upon request.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the

full case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table IA.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance

submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the

manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class

M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall

be provided with each lot of microcircuits delivered to this drawing.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-96523

SHEET

5962H9652301QCA Related Products

	5962H9652301QCA	5962H9652301QXC	5962H9652301VCC	5962H9652301QXA	5962H9652301VCA	5962H9652301QCC	5962H9652301VXC
Description	AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14	AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14	AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14	AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14	AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14	AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14	AND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14
package instruction	DIP, DIP14,.3	DFP, FL14,.3	DIP, DIP14,.3	DFP, FL14,.3	DIP, DIP14,.3	SIDE BRAZED, CERAMIC, DIP-14	DFP, FL14,.3
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A
series	ACT	ACT	ACT	ACT	ACT	ACT	ACT
JESD-30 code	R-XDIP-T14	R-XDFP-F14	R-XDIP-T14	R-XDFP-F14	R-XDIP-T14	R-XDIP-T14	R-XDFP-F14
JESD-609 code	e0	e4	e4	e0	e0	e4	e4
length	19.43 mm	9.525 mm	19.43 mm	9.525 mm	19.43 mm	19.43 mm	9.525 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE
MaximumI(ol)	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A
Number of functions	3	3	3	3	3	3	3
Number of entries	3	3	3	3	3	3	3
Number of terminals	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DFP	DIP	DFP	DIP	DIP	DFP
Encapsulate equivalent code	DIP14,.3	FL14,.3	DIP14,.3	FL14,.3	DIP14,.3	DIP14,.3	FL14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	FLATPACK	IN-LINE	FLATPACK	IN-LINE	IN-LINE	FLATPACK
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Sup	13 ns	13 ns	13 ns	13 ns	13 ns	13 ns	13 ns
propagation delay (tpd)	13 ns	13 ns	13 ns	13 ns	13 ns	13 ns	13 ns
Certification status	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO
Filter level	38535Q/M;38534H;883B	38535Q/M;38534H;883B	38535V;38534K;883S	38535Q/M;38534H;883B	38535V;38534K;883S	38535Q/M;38534H;883B	38535V;38534K;883S
Maximum seat height	5.08 mm	2.921 mm	5.08 mm	2.921 mm	5.08 mm	5.08 mm	2.921 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	NO	YES	NO	NO	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	TIN LEAD	GOLD	GOLD	TIN LEAD	TIN LEAD	GOLD	GOLD
Terminal form	THROUGH-HOLE	FLAT	THROUGH-HOLE	FLAT	THROUGH-HOLE	THROUGH-HOLE	FLAT
Terminal pitch	2.54 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
total dose	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V
width	7.62 mm	6.2865 mm	7.62 mm	6.2865 mm	7.62 mm	7.62 mm	6.2865 mm
Base Number Matches	1	1	1	1	1	1	1

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