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5962H9655602V9B

Description
Serial In Parallel Out, AC Series, 8-Bit, Right Direction, True Output, CMOS, DIE-14
Categorylogic    logic   
File Size409KB,26 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962H9655602V9B Overview

Serial In Parallel Out, AC Series, 8-Bit, Right Direction, True Output, CMOS, DIE-14

5962H9655602V9B Parametric

Parameter NameAttribute value
package instructionDIE, DIE OR CHIP
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
Counting directionRIGHT
seriesAC
JESD-30 codeR-XUUC-N14
JESD-609 codee0
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Maximum Frequency@Nom-Sup83000000 Hz
Number of digits8
Number of functions1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityTRUE
Package body materialUNSPECIFIED
encapsulated codeDIE
Encapsulate equivalent codeDIE OR CHIP
Package shapeRECTANGULAR
Package formUNCASED CHIP
power supply3.3/5 V
propagation delay (tpd)25 ns
Certification statusQualified
Filter levelMIL-PRF-38535 Class V
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal locationUPPER
total dose1M Rad(Si) V
Trigger typePOSITIVE EDGE
Base Number Matches1
REVISIONS
LTR
A
B
C
D
DESCRIPTION
Changes in accordance with NOR 5962-R104-97. – CFS
Changes in accordance with NOR 5962-R291-97. – CFS
Incorporate Revisions A and B. Update boilerplate to MIL-PRF-38535
requirements. – LTG
Add device types 02 and 03. Add test circuit to figure 4. Add die type B to
appendix A. Update boilerplate and editorial changes throughout. – LTG
Correct radiation features for device types 02 and 03 in section 1.5 and add
footnote 8/. Correct footnotes 2/ and 7/ in Table IA. Correct SEP test limits in
table IB. Correct paragraph 4.4.4.1. Update boilerplate paragraphs to current
MIL-PRF-38535 requirements.- MAA
Correct radiation features in section 1.5 and on table IA and table IB. - LTG
Add equivalent test circuits and footnote 5 to figure 4. Delete class M
requirements. - MAA
DATE (YR-MO-DA)
96-11-18
97-05-06
01-11-01
04-08-02
APPROVED
Monica L. Poelking
Monica L. Poelking
Thomas M. Hess
Thomas M. Hess
E
09-10-05
Thomas M. Hess
F
G
11-02-24
12-10-25
David Corbett
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
G
15
G
16
G
17
G
18
REV
SHEET
PREPARED BY
Thanh V. Nguyen
CHECKED BY
Thanh V. Nguyen
APPROVED BY
Monica L. Poelking
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DRAWING APPROVAL DATE
96-04-24
REVISION LEVEL
G
19
G
20
G
21
G
1
G
22
G
2
G
23
G
3
G
24
G
4
G
5
G
6
G
7
G
8
G
9
G
10
G
11
G
12
G
13
G
14
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED, ADVANCED CMOS, 8-BIT SERIAL-IN
/PARALLEL-OUT SHIFT REGISTER, MONOLITHIC
SILICON
SIZE
CAGE CODE
G
A
67268
SHEET
5962-96556
1 OF 24
DSCC FORM 2233
APR 97
5962-E020-13

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