PRELIMINARY DATA SHEET
256M bits AS SDRAM
EDS2516JEBH-75R3 (16M words
×
16 bits)
Description
The EDS2516JEBH-75R3 is a 256M bits AS SDRAM
(Application Specific SDRAM) organized as 4,194,304
words
×
16 bits
×
4 banks and specified suitable for
portable digital consumer electronics.
It is packaged in 54-ball FBGA.
Pin Configurations
/xxx indicate active low signal.
54-ball FBGA
1
A
VSS
DQ15 VSSQ
VDDQ
DQ0
VDD
2
3
4
5
6
7
8
9
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Features
•
•
•
•
•
•
2.5V power supply
Clock frequency: 133MHz (max.)
LVCMOS interface
Single pulsed /RAS
×16
organization
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8 and full
page
•
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
•
/CAS capability (CL): 3
•
Programmable driver strength: Half , Quarter
•
Byte control by UDQM and LDQM
•
Address
8K Row address /512 column address
•
Refresh cycles
8192 refresh cycles/16ms
•
Auto refresh capability
•
FBGA package with lead free solder (Sn-Ag-Cu)
RoHS compliant
B
DQ14 DQ13 VDDQ
VSSQ
DQ2
DQ1
C
DQ12 DQ11 VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
Document No. E0811E10 (Ver. 1.0)
Date Published September 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2005
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UDQM
CLK
CKE
/CAS
/RAS
/WE
G
A12
A11
A9
BA0
BA1
/CS
H
A8
A7
A6
A0
A1
A10
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VSS
A5
A4
A3
A2
VDD
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM /UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data input/ output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
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EDS2516JEBH-75R3
Ordering Information
Part number
EDS2516JEBH-75R3-E
Supply
voltage
2.5V
Organization
(words
×
bits) Internal Banks
16M
×
16
4
Clock frequency
MHz (max.)
133
/CAS latency
3
Package
54-ball FBGA
Part Number
E D S 25 16 J E BH - 75R3 - E
Elpida Memory
Type
D: Monolithic Device
Environment Code
E: Lead Free
EO
Product Family
S: SDRAM
Density / Bank
25: 256M/4-bank, 8K Rows
Organization
16: x16
Speed
75R3: 133MHz/CL3
Power Supply, Interface
J: 2.5V, LVCMOS
Die Rev.
Package
BH: FBGA(Board Type)
Preliminary Data Sheet E0811E10 (Ver. 1.0)
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EDS2516JEBH-75R3
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram ...............................................................................................................................................9
Pin Function.................................................................................................................................................10
Command Operation ...................................................................................................................................12
Simplified State Diagram .............................................................................................................................21
Mode Register and Extended Mode Register Configuration.......................................................................22
Power-up sequence.....................................................................................................................................24
Operation of the SDRAM.............................................................................................................................25
Timing Waveforms.......................................................................................................................................41
Package Drawing ........................................................................................................................................47
Recommended Soldering Conditions..........................................................................................................48
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Preliminary Data Sheet E0811E10 (Ver. 1.0)
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EDS2516JEBH-75R3
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–0.5 to +3.6
–0.5 to +3.6
50
1.0
–5 to +85
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
EO
Storage temperature
Parameter
Supply voltage
Input high voltage
Input low voltage
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = –5°C to +85°C)
Symbol
VDD, VDDQ
VSS, VSSQ
VIH
min.
2.3
0
1.8
–0.3
max.
2.7
0
VDD + 0.3
0.5
Unit
V
V
V
V
Notes
1
2
3
4
L
VIL
Notes: 1.
2.
3.
4.
The supply voltage with all VDD and VDDQ pins must be on the same level.
The supply voltage with all VSS and VSSQ pins must be on the same level.
The peak of VIH = VDD + 1.0V (pulse width at VIH (max.)
≤
3ns).
The bottom of VIL = VSS – 1.0V (pulse width at VIL (min.)
≤
3ns).
Preliminary Data Sheet E0811E10 (Ver. 1.0)
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EDS2516JEBH-75R3
DC Characteristics 1 (TA = –5°C to +85°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Operating current
Symbol
IDD1
Grade
max.
80
Unit
mA
Test condition
Burst length = 1
tRC = tRC (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE
≤
0.3V,
tCK = tCK (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE
≤
0.3V, tCK =
∞
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE, /CS = VIH,
tCK = tCK (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE = VIH, tCK =
∞,
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE
≤
VIL, tCK = tCK (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE
≤
VIL, tCK =
∞
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE, /CS = VIH, tCK = tCK (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE = VIH, tCK =
∞,
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
tCK = tCK (min.),
BL = 4
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
tRC = tRC (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
Notes
1, 2, 3
Standby current in power down
Standby current in power down
(input signal stable)
Standby current in non power down
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
4
3
20
9
4
4
20
15
70
180
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
EO
Burst operating current
Refresh current
Standby current in non power down
(input signal stable)
Active standby current in power down
Active standby current in power down
(input signal stable)
Active standby current in non power down IDD3N
Active standby current in non power down
IDD3NS
(input signal stable)
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E0811E10 (Ver. 1.0)
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