EDJ1104BDSE-DJ-F datasheet, PDF

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EDJ1104BDSE-DJ-F: Description1G bits DDR3 SDRAM; Categorystorage storage; File Size2MB，147 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en; Environmental Compliance

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EDJ1104BDSE-DJ-F Overview

1G bits DDR3 SDRAM

EDJ1104BDSE-DJ-F Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ELPIDA
Parts packaging code	BGA
package instruction	TFBGA, BGA78,9X13,32
Contacts	78
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.255 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	667 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B78
JESD-609 code	e1
length	10.6 mm
memory density	1073741824 bi
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	78
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA78,9X13,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	4,8
Maximum slew rate	0.31 mA
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm

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PRELIMINARY DATA SHEET

1G bits DDR3 SDRAM

EDJ1104BDSE (256M words

4 bits)

EDJ1108BDSE (128M words

8 bits)

Specifications

•

Density: 1G bits

•

Organization



32M words

4 bits

8 banks (EDJ1104BDSE)



16M words

8 bits

8 banks (EDJ1108BDSE)

•

Package



78-ball FBGA



Lead-free (RoHS compliant) and Halogen-free

•

Power supply: VDD, VDDQ

1.5V

0.075V

•

Data rate



1600Mbps/1333Mbps/1066Mbps (max.)

•

1KB page size



Row address: A0 to A13



Column address: A0 to A9, A11 (EDJ1104BDSE)

A0 to A9 (EDJ1108BDSE)

•

Eight internal banks for concurrent operation

•

Interface: SSTL_15

•

Burst lengths (BL): 8 and 4 with Burst Chop (BC)

•

Burst type (BT):



Sequential (8, 4 with BC)



Interleave (8, 4 with BC)

•

/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

•

/CAS Write Latency (CWL): 5, 6, 7, 8

•

Precharge: auto precharge option for each burst

access

•

Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

•

Refresh: auto-refresh, self-refresh

Features

•

Double-data-rate architecture; two data transfers per

clock cycle

•

The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

•

Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

•

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

•

Data mask (DM) for write data

•

Posted /CAS by programmable additive latency for

better command and data bus efficiency

•

On-Die Termination (ODT) for better signal quality



Synchronous ODT



Dynamic ODT



Asynchronous ODT

•

Multi Purpose Register (MPR) for temperature read

out

•

ZQ calibration for DQ drive and ODT

•

Programmable Partial Array Self-Refresh (PASR)

•

/RESET pin for Power-up sequence and reset

function

•

SRT range:



Normal/extended

•

Programmable Output driver impedance control

•

Refresh cycles



Average refresh period

7.8µs at 0°C

≤

≤ +85°C

3.9µs at

+85°C <

≤ +95°C

•

Operating case temperature range



TC = 0°C to +95°C

Document No. E1494E50 (Ver. 5.0)

Date Published July 2009 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida

Memory, Inc. 2009

EDJ1104BDSE, EDJ1108BDSE

CONTENTS

Specifications.................................................................................................................................................1

Features.........................................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Pin Configurations .........................................................................................................................................3

Electrical Conditions ......................................................................................................................................6

Absolute Maximum Ratings .......................................................................................................................... 6

Operating Temperature Condition ................................................................................................................ 6

Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) ................... 7

AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V)....................... 7

VREF Tolerances ......................................................................................................................................... 8

Input Slew Rate Derating .............................................................................................................................. 9

AC and DC Logic Input Levels for Differential Signals ................................................................................ 15

AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) .................. 20

AC Overshoot/Undershoot Specification..................................................................................................... 22

Output Driver Impedance............................................................................................................................ 23

On-Die Termination (ODT) Levels and I-V Characteristics ......................................................................... 25

ODT Timing Definitions............................................................................................................................... 27

IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) ................................... 31

Electrical Specifications...............................................................................................................................44

DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) ................................................. 44

DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) ................................................. 45

Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V

0.075V) ..................................................................... 46

Standard Speed Bins .................................................................................................................................. 47

AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V, VSS, VSSQ = 0V)....................... 50

Block Diagram .............................................................................................................................................64

Pin Function.................................................................................................................................................65

Command Operation ...................................................................................................................................67

Command Truth Table ................................................................................................................................ 67

CKE Truth Table ......................................................................................................................................... 71

Simplified State Diagram .............................................................................................................................72

RESET and Initialization Procedure ............................................................................................................73

Power-Up and Initialization Sequence ........................................................................................................ 73

Reset and Initialization with Stable Power .................................................................................................. 74

Programming the Mode Register.................................................................................................................75

Mode Register Set Command Cycle Time (tMRD) ..................................................................................... 75

MRS Command to Non-MRS Command Delay (tMOD) ............................................................................. 75

DDR3 SDRAM Mode Register 0 [MR0] ...................................................................................................... 76

DDR3 SDRAM Mode Register 1 [MR1] ...................................................................................................... 77

Preliminary Data Sheet E1494E50 (Ver. 5.0)

EDJ1104BDSE, EDJ1108BDSE

DDR3 SDRAM Mode Register 1 [MR1] ...................................................................................................... 77

DDR3 SDRAM Mode Register 2 [MR2] ...................................................................................................... 78

DDR3 SDRAM Mode Register 3 [MR3] ...................................................................................................... 79

Burst Length (MR0) .................................................................................................................................... 80

Burst Type (MR0) ....................................................................................................................................... 80

DLL Enable (MR1) ...................................................................................................................................... 81

DLL-off Mode .............................................................................................................................................. 81

DLL on/off switching procedure .................................................................................................................. 82

Additive Latency (MR1)............................................................................................................................... 84

Write Leveling (MR1) .................................................................................................................................. 85

TDQS, /TDQS function (MR1) .................................................................................................................... 88

Extended Temperature Usage (MR2) ......................................................................................................... 89

Multi Purpose Register (MR3)..................................................................................................................... 91

Operation of the DDR3 SDRAM ..................................................................................................................98

Read Timing Definition................................................................................................................................ 98

Read Operation ........................................................................................................................................ 102

Write Timing Definition.............................................................................................................................. 109

Write Operation......................................................................................................................................... 110

Write Timing Violations ............................................................................................................................. 116

Write Data Mask ....................................................................................................................................... 117

Precharge ................................................................................................................................................. 118

Auto Precharge Operation ........................................................................................................................ 119

Auto-Refresh............................................................................................................................................. 120

Self-Refresh.............................................................................................................................................. 121

Power-Down Mode ................................................................................................................................... 122

Input Clock Frequency Change during Precharge Power-Down............................................................... 129

On-Die Termination (ODT)........................................................................................................................ 130

ZQ Calibration........................................................................................................................................... 142

Package Drawing ......................................................................................................................................144

78-ball FBGA ............................................................................................................................................ 144

Recommended Soldering Conditions........................................................................................................145

Preliminary Data Sheet E1494E50 (Ver. 5.0)

EDJ1104BDSE-DJ-F Related Products

	EDJ1104BDSE-DJ-F	EDJ1108BDSE-GN-F	EDJ1108BDSE	EDJ1108BDSE-DJ-F	EDJ1108BDSE-AE-F	EDJ1104BDSE-GL-F	EDJ1104BDSE-AE-F	EDJ1104BDSE
Description	1G bits DDR3 SDRAM	1G bits DDR3 SDRAM	1G bits DDR3 SDRAM	1G bits DDR3 SDRAM	1G bits DDR3 SDRAM	1G bits DDR3 SDRAM	1G bits DDR3 SDRAM	1G bits DDR3 SDRAM
Is it Rohs certified?	conform to	conform to	-	conform to	conform to	conform to	conform to	-
Maker	ELPIDA	ELPIDA	-	ELPIDA	ELPIDA	ELPIDA	ELPIDA	-
Parts packaging code	BGA	BGA	-	BGA	BGA	BGA	BGA	-
package instruction	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	-	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	-
Contacts	78	78	-	78	78	78	78	-
Reach Compliance Code	unknow	unknow	-	unknown	unknow	unknow	unknow	-
ECCN code	EAR99	EAR99	-	EAR99	EAR99	EAR99	EAR99	-
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	-	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	-
Maximum access time	0.255 ns	0.225 ns	-	0.255 ns	0.3 ns	0.225 ns	0.3 ns	-
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-
Maximum clock frequency (fCLK)	667 MHz	800 MHz	-	667 MHz	533 MHz	800 MHz	533 MHz	-
I/O type	COMMON	COMMON	-	COMMON	COMMON	COMMON	COMMON	-
interleaved burst length	4,8	4,8	-	4,8	4,8	4,8	4,8	-
JESD-30 code	R-PBGA-B78	R-PBGA-B78	-	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	-
JESD-609 code	e1	e1	-	e1	e1	e1	e1	-
length	10.6 mm	10.6 mm	-	10.6 mm	10.6 mm	10.6 mm	10.6 mm	-
memory density	1073741824 bi	1073741824 bi	-	1073741824 bit	1073741824 bi	1073741824 bi	1073741824 bi	-
Memory IC Type	DDR DRAM	DDR DRAM	-	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	-
memory width	4	8	-	8	8	4	4	-
Number of functions	1	1	-	1	1	1	1	-
Number of ports	1	1	-	1	1	1	1	-
Number of terminals	78	78	-	78	78	78	78	-
word count	268435456 words	134217728 words	-	134217728 words	134217728 words	268435456 words	268435456 words	-
character code	256000000	128000000	-	128000000	128000000	256000000	256000000	-
Operating mode	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-
Maximum operating temperature	85 °C	85 °C	-	85 °C	85 °C	85 °C	85 °C	-
organize	256MX4	128MX8	-	128MX8	128MX8	256MX4	256MX4	-
Output characteristics	3-STATE	3-STATE	-	3-STATE	3-STATE	3-STATE	3-STATE	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TFBGA	TFBGA	-	TFBGA	TFBGA	TFBGA	TFBGA	-
Encapsulate equivalent code	BGA78,9X13,32	BGA78,9X13,32	-	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	-
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	-	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	-
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
power supply	1.5 V	1.5 V	-	1.5 V	1.5 V	1.5 V	1.5 V	-
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
refresh cycle	8192	8192	-	8192	8192	8192	8192	-
Maximum seat height	1.2 mm	1.2 mm	-	1.2 mm	1.2 mm	1.2 mm	1.2 mm	-
self refresh	YES	YES	-	YES	YES	YES	YES	-
Continuous burst length	4,8	4,8	-	4,8	4,8	4,8	4,8	-
Maximum slew rate	0.31 mA	0.35 mA	-	0.31 mA	0.27 mA	0.35 mA	0.27 mA	-
Maximum supply voltage (Vsup)	1.575 V	1.575 V	-	1.575 V	1.575 V	1.575 V	1.575 V	-
Minimum supply voltage (Vsup)	1.425 V	1.425 V	-	1.425 V	1.425 V	1.425 V	1.425 V	-
Nominal supply voltage (Vsup)	1.5 V	1.5 V	-	1.5 V	1.5 V	1.5 V	1.5 V	-
surface mount	YES	YES	-	YES	YES	YES	YES	-
technology	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS	-
Temperature level	OTHER	OTHER	-	OTHER	OTHER	OTHER	OTHER	-
Terminal form	BALL	BALL	-	BALL	BALL	BALL	BALL	-
Terminal pitch	0.8 mm	0.8 mm	-	0.8 mm	0.8 mm	0.8 mm	0.8 mm	-
Terminal location	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
width	7.5 mm	7.5 mm	-	7.5 mm	7.5 mm	7.5 mm	7.5 mm	-

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