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EDJ1104BDSE

Description
1G bits DDR3 SDRAM
File Size2MB，147 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
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EDJ1104BDSE Overview

1G bits DDR3 SDRAM

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PRELIMINARY DATA SHEET
1G bits DDR3 SDRAM
EDJ1104BDSE (256M words
×
4 bits)
EDJ1108BDSE (128M words
×
8 bits)
Specifications
•
Density: 1G bits
•
Organization
32M words
×
4 bits
×
8 banks (EDJ1104BDSE)
16M words
×
8 bits
×
8 banks (EDJ1108BDSE)
•
Package
78-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: VDD, VDDQ
=
1.5V
±
0.075V
•
Data rate
1600Mbps/1333Mbps/1066Mbps (max.)
•
1KB page size
Row address: A0 to A13
Column address: A0 to A9, A11 (EDJ1104BDSE)
A0 to A9 (EDJ1108BDSE)
•
Eight internal banks for concurrent operation
•
Interface: SSTL_15
•
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
•
Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
•
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
•
/CAS Write Latency (CWL): 5, 6, 7, 8
•
Precharge: auto precharge option for each burst
access
•
Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
•
Refresh: auto-refresh, self-refresh
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
•
Multi Purpose Register (MPR) for temperature read
out
•
ZQ calibration for DQ drive and ODT
•
Programmable Partial Array Self-Refresh (PASR)
•
/RESET pin for Power-up sequence and reset
function
•
SRT range:
Normal/extended
•
Programmable Output driver impedance control
•
Refresh cycles
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Document No. E1494E50 (Ver. 5.0)
Date Published July 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2009

EDJ1104BDSE Related Products

EDJ1104BDSE EDJ1108BDSE-GN-F EDJ1108BDSE EDJ1108BDSE-DJ-F EDJ1108BDSE-AE-F EDJ1104BDSE-GL-F EDJ1104BDSE-DJ-F EDJ1104BDSE-AE-F
Description 1G bits DDR3 SDRAM 1G bits DDR3 SDRAM 1G bits DDR3 SDRAM 1G bits DDR3 SDRAM 1G bits DDR3 SDRAM 1G bits DDR3 SDRAM 1G bits DDR3 SDRAM 1G bits DDR3 SDRAM
Is it Rohs certified? - conform to - conform to conform to conform to conform to conform to
Maker - ELPIDA - ELPIDA ELPIDA ELPIDA ELPIDA ELPIDA
Parts packaging code - BGA - BGA BGA BGA BGA BGA
package instruction - TFBGA, BGA78,9X13,32 - TFBGA, BGA78,9X13,32 TFBGA, BGA78,9X13,32 TFBGA, BGA78,9X13,32 TFBGA, BGA78,9X13,32 TFBGA, BGA78,9X13,32
Contacts - 78 - 78 78 78 78 78
Reach Compliance Code - unknow - unknown unknow unknow unknow unknow
ECCN code - EAR99 - EAR99 EAR99 EAR99 EAR99 EAR99
access mode - MULTI BANK PAGE BURST - MULTI BANK PAGE BURST MULTI BANK PAGE BURST MULTI BANK PAGE BURST MULTI BANK PAGE BURST MULTI BANK PAGE BURST
Maximum access time - 0.225 ns - 0.255 ns 0.3 ns 0.225 ns 0.255 ns 0.3 ns
Other features - AUTO/SELF REFRESH - AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
Maximum clock frequency (fCLK) - 800 MHz - 667 MHz 533 MHz 800 MHz 667 MHz 533 MHz
I/O type - COMMON - COMMON COMMON COMMON COMMON COMMON
interleaved burst length - 4,8 - 4,8 4,8 4,8 4,8 4,8
JESD-30 code - R-PBGA-B78 - R-PBGA-B78 R-PBGA-B78 R-PBGA-B78 R-PBGA-B78 R-PBGA-B78
JESD-609 code - e1 - e1 e1 e1 e1 e1
length - 10.6 mm - 10.6 mm 10.6 mm 10.6 mm 10.6 mm 10.6 mm
memory density - 1073741824 bi - 1073741824 bit 1073741824 bi 1073741824 bi 1073741824 bi 1073741824 bi
Memory IC Type - DDR DRAM - DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM
memory width - 8 - 8 8 4 4 4
Number of functions - 1 - 1 1 1 1 1
Number of ports - 1 - 1 1 1 1 1
Number of terminals - 78 - 78 78 78 78 78
word count - 134217728 words - 134217728 words 134217728 words 268435456 words 268435456 words 268435456 words
character code - 128000000 - 128000000 128000000 256000000 256000000 256000000
Operating mode - SYNCHRONOUS - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature - 85 °C - 85 °C 85 °C 85 °C 85 °C 85 °C
organize - 128MX8 - 128MX8 128MX8 256MX4 256MX4 256MX4
Output characteristics - 3-STATE - 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material - PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - TFBGA - TFBGA TFBGA TFBGA TFBGA TFBGA
Encapsulate equivalent code - BGA78,9X13,32 - BGA78,9X13,32 BGA78,9X13,32 BGA78,9X13,32 BGA78,9X13,32 BGA78,9X13,32
Package shape - RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form - GRID ARRAY, THIN PROFILE, FINE PITCH - GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius) - NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply - 1.5 V - 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V
Certification status - Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
refresh cycle - 8192 - 8192 8192 8192 8192 8192
Maximum seat height - 1.2 mm - 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
self refresh - YES - YES YES YES YES YES
Continuous burst length - 4,8 - 4,8 4,8 4,8 4,8 4,8
Maximum slew rate - 0.35 mA - 0.31 mA 0.27 mA 0.35 mA 0.31 mA 0.27 mA
Maximum supply voltage (Vsup) - 1.575 V - 1.575 V 1.575 V 1.575 V 1.575 V 1.575 V
Minimum supply voltage (Vsup) - 1.425 V - 1.425 V 1.425 V 1.425 V 1.425 V 1.425 V
Nominal supply voltage (Vsup) - 1.5 V - 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V
surface mount - YES - YES YES YES YES YES
technology - CMOS - CMOS CMOS CMOS CMOS CMOS
Temperature level - OTHER - OTHER OTHER OTHER OTHER OTHER
Terminal form - BALL - BALL BALL BALL BALL BALL
Terminal pitch - 0.8 mm - 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location - BOTTOM - BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
Maximum time at peak reflow temperature - NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width - 7.5 mm - 7.5 mm 7.5 mm 7.5 mm 7.5 mm 7.5 mm

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