PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EDD2508AKTA (32M words
×
8 bits)
Description
The EDD2508AK is a 256M bits DDR SDRAM
organized as 8,388,608 words
×
8 bits
×
4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
They are packaged in standard 66-pin plastic TSOP
(II).
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
EO
Features
•
2.5 V power supply : VDDQ = 2.5V
±
0.2V
: VDD = 2.5V
±
0.2V
•
Data rate: 333Mbps (max.)
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs, outputs, and DM are synchronized with
DQS
•
4 internal banks for concurrent operation
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
2.5 V (SSTL_2 compatible) I/O
•
Programmable burst length (BL): 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Programmable output driver strength: normal/weak
•
Refresh cycles: 8192 refresh cycles/64ms
⎯
7.8μs maximum average periodic refresh interval
•
2 variations of refresh
⎯
Auto refresh
⎯
Self refresh
Document No. E0380E10 (Ver. 1.0)
Date Published May 2003 (K) Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2003
L
od
Pr
A0 to A12
BA0, BA1
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
DQ0 to DQ7
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
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EDD2508AKTA
Ordering Information
Part number
EDD2508AKTA-6B
Mask
version
K
Organization
(words
×
bits)
32M
×
8
Internal
banks
4
Data rate
Mbps (max.)
333
JEDEC speed bin
(CL-tRCD-tRP)
DDR333B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 25 08 A K TA - 6B
Elpida Memory
EO
Type
D: Monolithic Device
Product Code
D: DDR SDRAM
Density / Bank
25: 256M / 4-bank
Bit Organization
8: x8
Voltage, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
TA: TSOP (II)
Speed
6B: DDR333B (2.5-3-3)
Preliminary Data Sheet E0380E10 (Ver. 1.0)
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EDD2508AKTA
CONTENTS
Description .................................................................................................................................................... 1
Features ........................................................................................................................................................ 1
Pin Configurations......................................................................................................................................... 1
Ordering Information ..................................................................................................................................... 2
Part Number.................................................................................................................................................. 2
Electrical Specifications ................................................................................................................................ 4
Block Diagram............................................................................................................................................. 10
Pin Function ................................................................................................................................................ 11
Command Operation................................................................................................................................... 13
Simplified State Diagram ............................................................................................................................ 21
Operation of the DDR SDRAM ................................................................................................................... 22
Timing Waveforms ...................................................................................................................................... 41
Package Drawing........................................................................................................................................ 47
Recommended Soldering Conditions ......................................................................................................... 48
EO
Preliminary Data Sheet E0380E10 (Ver. 1.0)
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EDD2508AKTA
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–1.0 to +3.6
–1.0 to +3.6
50
1.0
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
EO
Parameter
Supply voltage
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
Input voltage level,
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Symbol
VDD,
VDDQ
VSS,
VSSQ
VREF
VTT
Min
2.3
0
0.49
×
VDDQ
VREF – 0.04
Typ
2.5
0
0.50
×
VDDQ
VREF
—
Max
2.7
0
0.51
×
VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
Unit
V
V
V
V
V
V
V
2
3
4
Notes
1
L
VIH (DC)
VIL (DC)
VIN (DC)
VIX (DC)
VID (DC)
od
Pr
VREF + 0.15
–0.3
—
–0.3
—
0.5
×
VDDQ
−
0.2V
0.36
0.5
×
VDDQ
—
VDDQ + 0.3
0.5
×
VDDQ + 0.2V V
VDDQ + 0.6
V
5, 6
Notes: 1.
2.
3.
4.
5.
6.
VDDQ must be lower than or equal to VDD.
VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
VIN (DC) specifies the allowable DC execution of each differential input.
VID (DC) specifies the input differential voltage required for switching.
VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
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Preliminary Data Sheet E0380E10 (Ver. 1.0)
4
EDD2508AKTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
max.
Parameter
Symbol
Grade
-6B
-6B
-6B
-6B
-6B
-6B
-6B
-6B
-6B
-6B
-6B
×
8
95
125
3
25
20
20
55
185
185
170
3
320
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
CKE
≥
VIH,
tRC = tRC (min.)
CKE
≥
VIH, BL = 4, CL = 2.5,
tRC = tRC (min.)
CKE
≤
VIL
CKE
≥
VIH, /CS
≥
VIH
DQ, DQS, DM = VREF
CKE
≥
VIH, /CS
≥
VIH
DQ, DQS, DM = VREF
CKE
≤
VIL
CKE
≥
VIH, /CS
≥
VIH
tRAS = tRAS (max.)
CKE
≥
VIH, BL = 2, CL = 2.5
CKE
≥
VIH, BL = 2, CL = 2.5
tRFC = tRFC (min.),
Input
≤
VIL or
≥
VIH
Input
≥
VDD – 0.2 V
Input
≤
0.2 V
BL = 4
5, 6, 7
Notes
1, 2, 9
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
Operating current (ACT-PRE) IDD0
Operating current
(ACT-READ-PRE)
Idle power down standby
current
Floating idle standby current
Quiet idle standby current
Active power down standby
current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto Refresh current
Self refresh current
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
EO
Operating current
(4 banks interleaving)
Parameter
Input leakage current
Output leakage current
Output high current
Output low current
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at
≥
VIH or
≤
VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Symbol
ILI
ILO
IOH
IOL
min.
max.
Unit
Preliminary Data Sheet E0380E10 (Ver. 1.0)
L
IDD7A
-6B
–2
–5
od
Pr
2
µA
5
µA
–15.2
15.2
—
mA
—
mA
Test condition
Notes
VDD
≥
VIN
≥
VSS
VDDQ
≥
VOUT
≥
VSS
VOUT = 1.95V
VOUT = 0.35V
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