EDD2508AKTA datasheet, PDF - EEWORLD Datasheet

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EDD2508AKTA: Description256M bits DDR SDRAM; File Size456KB，50 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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EDD2508AKTA Overview

256M bits DDR SDRAM

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PRELIMINARY DATA SHEET

256M bits DDR SDRAM

EDD2508AKTA (32M words

8 bits)

Description

The EDD2508AK is a 256M bits DDR SDRAM

organized as 8,388,608 words

8 bits

4 banks.

Read and write operations are performed at the cross

points of the CK and the /CK. This high-speed data

transfer is realized by the 2 bits prefetch-pipelined

architecture. Data strobe (DQS) both for read and

write are available for high speed and reliable data bus

design. By setting extended mode resistor, the on-chip

Delay Locked Loop (DLL) can be set enable or disable.

They are packaged in standard 66-pin plastic TSOP

(II).

Pin Configurations

/xxx indicates active low signal.

66-pin Plastic TSOP(II)

VDD

DQ0

VDDQ

DQ1

VSSQ

DQ2

VDDQ

DQ3

VSSQ

VDDQ

VDD

/WE

/CAS

/RAS

/CS

BA0

BA1

A10(AP)

VDD

VSS

DQ7

VSSQ

DQ6

VDDQ

DQ5

VSSQ

DQ4

VDDQ

VSSQ

DQS

VREF

VSS

/CK

CKE

A12

A11

VSS

Features

•

2.5 V power supply : VDDQ = 2.5V

0.2V

: VDD = 2.5V

0.2V

•

Data rate: 333Mbps (max.)

•

Double Data Rate architecture; two data transfers per

clock cycle

•

Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

•

Data inputs, outputs, and DM are synchronized with

DQS

•

4 internal banks for concurrent operation

•

DQS is edge aligned with data for READs; center

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

•

Data mask (DM) for write data

•

Auto precharge option for each burst access

•

2.5 V (SSTL_2 compatible) I/O

•

Programmable burst length (BL): 2, 4, 8

•

Programmable /CAS latency (CL): 2, 2.5

•

Programmable output driver strength: normal/weak

•

Refresh cycles: 8192 refresh cycles/64ms

⎯

7.8μs maximum average periodic refresh interval

•

2 variations of refresh

⎯

Auto refresh

⎯

Self refresh

Document No. E0380E10 (Ver. 1.0)

Date Published May 2003 (K) Japan

URL: http://www.elpida.com

©Elpida

Memory, Inc. 2003

A0 to A12

BA0, BA1

DQS

/CS

/RAS

/CAS

/WE

/CK

CKE

VREF

VDD

VSS

VDDQ

VSSQ

DQ0 to DQ7

(Top view)

Address input

Bank select address

Data-input/output

Input and output data strobe

Chip select

Row address strobe command

Column address strobe command

Write enable

Input mask

Clock input

Differential clock input

Clock enable

Input reference voltage

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

EDD2508AKTA

CONTENTS

Description .................................................................................................................................................... 1

Features ........................................................................................................................................................ 1

Pin Configurations......................................................................................................................................... 1

Ordering Information ..................................................................................................................................... 2

Part Number.................................................................................................................................................. 2

Electrical Specifications ................................................................................................................................ 4

Block Diagram............................................................................................................................................. 10

Pin Function ................................................................................................................................................ 11

Command Operation................................................................................................................................... 13

Simplified State Diagram ............................................................................................................................ 21

Operation of the DDR SDRAM ................................................................................................................... 22

Timing Waveforms ...................................................................................................................................... 41

Package Drawing........................................................................................................................................ 47

Recommended Soldering Conditions ......................................................................................................... 48

Preliminary Data Sheet E0380E10 (Ver. 1.0)

EDD2508AKTA Related Products

	EDD2508AKTA	EDD2508AKTA-6B
Description	256M bits DDR SDRAM	256M bits DDR SDRAM

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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