5962-8601601QA datasheet, PDF - EEWORLD Datasheet

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5962-8601601QA: Description16-BIT, 5 MHz, MICROPROCESSOR, CDIP40; Categorysemiconductor The embedded processor and controller; File Size255KB，32 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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16-BIT, 5 MHz, MICROPROCESSOR, CDIP40

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80C88

March 1997

CMOS 8/16-Bit Microprocessor

Description

The Intersil 80C88 high performance 8/16-bit CMOS CPU is

manufactured using a self-aligned silicon gate CMOS pro-

cess (Scaled SAJI IV). Two modes of operation, MINimum

for small systems and MAXimum for larger applications such

as multiprocessing, allow user conﬁguration to achieve the

highest performance level.

Full TTL compatibility (with the exception of CLOCK) and

industry-standard operation allow use of existing NMOS

8088 hardware and Intersil CMOS peripherals.

Complete software compatibility with the 80C86, 8086, and

8088 microprocessors allows use of existing software in new

designs.

Features

• Compatible with NMOS 8088

• Direct Software Compatibility with 80C86, 8086, 8088

• 8-Bit Data Bus Interface; 16-Bit Internal Architecture

• Completely Static CMOS Design

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)

• Low Power Operation

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum

- ICCOP . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum

• 1 Megabyte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word, and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

• Bus-Hold Circuitry Eliminates Pull-up Resistors

• Wide Operating Temperature Ranges

- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . 0

C to + 70

- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to +85

- M80C88 . . . . . . . . . . . . . . . . . . . . . . . -55

C to +125

[ /Title

(80C88

)

/Sub-

ject

(CMO

S 8/16-

Bit

Micro-

proces-

sor)

/Autho

r ()

/Key-

words

(Inter-

sil

Corpo-

ration,

8/16

Bit uP,

micro-

proces-

sor, 8

bit, 16

bit, 8-

bit, 16-

bit,

8088,

PC)

/Cre-

ator ()

Ordering Information

PACKAGE

Plastic DIP

TEMPERATURE RANGE

C to +70

-40

C to +85

PLCC

C to +70

-40

C to +85

CERDIP

C to +70

-40

C to +85

-55

C to +125

SMD#

LCC

SMD#

-55

C to +125

-55

C to +125

-55

C to +125

CP80C88

IP80C88

CS80C88

lS80C88

CD80C88

ID80C88

MD80C88/B

5962-8601601QA

MR80C88/B

5962-8601601XA

5MHz

8MHz

CP80C88-2

IP80C88-2

CS80C88-2

IS80C88-2

CD80C88-2

ID80C88-2

MD80C88-2/B

MR80C88-2/B

PKG. NO.

E40.6

N44.65

F40.6

J44.A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

File Number

2949.1

3-1

80C88

Pin Description

The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these

descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers).

SYMBOL

AD7-AD0

NUMBER

9-16

TYPE

I/O

DESCRIPTION

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and

data (T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last

valid level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”

ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4).

These lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held

at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold

acknowledge” or “grant sequence”.

ADDRESS/STATUS: During T1, these are the four most

signiﬁcant address lines for memory operations. During

I/O operations, these lines are LOW. During memory and

I/O operations, status information is available on these

lines during T2, T3, TW and T4. S6 is always LOW. The

status of the interrupt enable ﬂag bit (S5) is updated at the

beginning of each clock cycle. S4 and S3 are encoded as

shown.

This information indicates which segment register is

presently being used for data accessing.

These lines are held at high impedance to the last valid

logic level during local bus “hold acknowledge” or “grant

Sequence”.

CHARACTERISTICS

Alternate Data

Stack

Code or None

Data

A15-A8

2-8, 39

A19/S6,

A18/S5,

A17/S4,

A16/S3

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depend-

ing on the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88

local bus. RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH

in T2 until the 80C88 local bus has ﬂoated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

READY: is the acknowledgment from the address memory or I/O device that it will complete the data

transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from

READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation

is not guaranteed if the set up and hold times are not met.

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of

each instruction to determine if the processor should enter into an interrupt acknowledge operation.

A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be

internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This

signal is active HIGH.

TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution con-

tinues, otherwise the processor waits in an “idle” state. This input is synchronized internally during

each clock cycle on the leading edge of CLK.

NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A sub-

routine is vectored to via an interrupt vector lookup table located in system memory. NMI is not

maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end

of the current instruction. This input is internally synchronized.

RESET: cases the processor to immediately terminate its present activity. The signal must transition

LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as de-

scribed in the instruction set description, when RESET returns LOW. RESET is internally synchro-

nized.

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33%

duty cycle to provide optimized internal timing.

: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for de-

coupling.

GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor be-

tween pins 1 and 20 is recommended for decoupling.

READY

INTR

TEST

NMI

RESET

CLK

GND

MN/MX

1, 20

33‘

MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are

discussed in the following sections.

3-4

80C88

Pin Description

(Continued)

The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = V

). Only the pin functions

which are unique to the minimum mode are described; all other pin functions are as described above.

MINIMUM MODE SYSTEM

NUMBER

SYMBOL

IO/M

TYPE

DESCRIPTION

STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from

an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the ﬁnal

T4 of the cycle (I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus

“hold acknowledge”.

Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depend-

ing on the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active

LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and

Tw of each interrupt acknowledge cycle. Note that INTA is never ﬂoated.

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the

82C82/82C83 address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note

that ALE is never ﬂoated.

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87

data bus transceiver. It is used to control the direction of data ﬂow through the transceiver. Logically,

DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH,

R = LOW). This signal is held to a high impedance logic one during local bus “hold acknowledge”.

DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which

uses the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles.

For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write

cycle, it is active from the beginning of T2 until the middle of T4. DEN is held to high impedance logic

one during local bus “hold acknowledge”.

HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD

must be active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an

acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA

the processor will ﬂoat the local bus and control lines. After HOLD is detected as being LOW, the

processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the

local bus and control lines.

Hold is not an asynchronous input. External synchronization should be provided if the system cannot

otherwise guarantee the set up time.

STATUS LINE: is logically equivalent to S0

in the maximum mode. The combination of

SS0, IO/M and DT/R allows the system to

completely decode the current bus cycle

status. SS0 is held to high impedance logic

one during local bus “hold acknowledge”.

IO/M

DT/R

SS0

CHARACTERISTICS

Interrupt Acknowledge

Read I/O Port

Write I/O Port

Halt

Code Access

Read Memory

Write Memory

Passive

INTA

ALE

DT/R

DEN

HOLD,

HLDA

SS0

3-5

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