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PUMA67S4000ALI-020

Description
SRAM Module, 128KX32, 20ns, CMOS, CQCC68, JLCC-68
Categorystorage    storage   
File Size303KB,10 Pages
ManufacturerMOSAIC
Websitehttp://www.mosaicsemi.com/
Download Datasheet Parametric View All

PUMA67S4000ALI-020 Overview

SRAM Module, 128KX32, 20ns, CMOS, CQCC68, JLCC-68

PUMA67S4000ALI-020 Parametric

Parameter NameAttribute value
MakerMOSAIC
Parts packaging codeLCC
package instruction,
Contacts68
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time20 ns
Other featuresCONFIGURABLE AS 512K X 8
Spare memory width16
JESD-30 codeS-CQCC-J68
memory density4194304 bit
Memory IC TypeSRAM MODULE
memory width32
Number of functions1
Number of terminals68
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formJ BEND
Terminal locationQUAD
Base Number Matches1
128K x 32 SRAM Module
PUMA 2/67/77S4000/A-020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (001) 858 674 2233, Fax No: (001) 858 674 2230
Issue 4.3 : December 1999
Description
Features
4 Megabit SRAM module.
Fast Access Times of 20/25/35 ns.
Output Configurable as 32 / 16 / 8 bit wide.
Upgradeable footprint.
Operating Power 3740 / 2310 / 1595 mW (Max).
Low Power Standby (L version) 220 mW (Max).
3.0V Battery Back-up Capability.
TTL Compatible Inputs and Outputs.
May be screened in accordance with MIL-STD-883.
PUMA 2 - 66 pin ceramic PGA.
PUMA 67 - 68 pin ceramic JLCC.
PUMA 77 - 68 pin ceramic Gullwing.
Available in PGA (PUMA 2), JLCC (PUMA 67) and
Gullwing (PUMA 77) footprints. The PUMA **S4000
is a 4 Mbit SRAM module, user configurable as
128K x 32, 256K x 16 or 512K x 8. The device is
available with fast access times of 20, 25 and 30ns.
A low power standby and Data Retention mode is
available. The device may be screened in
accordance with MIL-STD-883C.
Block Diagram
PUMA 2S4000, 67S4000A and 77S4000A
A0~A16
OE
WE4
WE3
WE2
WE1
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
Block Diagram
PUMA 67S4000 and 77S4000
A0-A16
OE
WE
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0-7
D8-15
D16-23
D24-31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
Pin Functions
A0~A16
CS1~4
OE
GND
Address Input
Chip Select
Output Enable
Ground
D0~D31
WE1~4
Vcc
Data Inputs/Outputs
Write Enables
Power (+5V)
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