PRELIMINARY DATA SHEET
2GB Unbuffered DDR2 SDRAM DIMM
EBE21UE8AEFB (256M words
×
64 bits, 2 Ranks)
Specifications
•
Density: 2GB
•
Organization
256M words
×
64 bits, 2 ranks
•
Mounting 16 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
•
Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
(EBE21UE8AEFB-xx-E)
Lead-free (RoHS compliant) and Halogen-free
(EBE21UE8AEFB-xx-F)
•
Power supply: VDD
=
1.8V
±
0.1V
•
Data rate: 800Mbps/667Mbps (max.)
•
Eight internal banks for concurrent operation
(components)
•
Interface: SSTL_18
•
Burst lengths (BL): 4, 8
•
/CAS Latency (CL): 3, 4, 5, 6
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E1401E10 (Ver. 1.0)
Date Published October 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2008
EBE21UE8AEFB
Pin Description
Pin name
A0 to A13
A10 (AP)
BA0, BA1, BA2
DQ0 to DQ63
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS7, /DQS0 to /DQS7
DM0 to DM7
SCL
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
ODT0, ODT1
NC
Function
Address input
Row address
Column address
Auto precharge
Bank select address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
ODT control
No connection
A0 to A13
A0 to A9
Preliminary Data Sheet E1401E10 (Ver. 1.0)
4
EBE21UE8AEFB
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
Voltage interface level of this
assembly
DDR SDRAM cycle time, CL = X
-8G (CL = 6)
-6E (CL = 5)
10
SDRAM access from clock (tAC)
-8G
-6E
11
12
13
14
15
16
17
18
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
Reserved
Bit7
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Bit6
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
Bit5
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
Bit4
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
1
Bit3
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
1
0
0
1
0
Bit2
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
1
0
Bit1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
Bit0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
0
Hex value Comments
80H
08H
08H
0EH
0AH
61H
40H
00H
05H
25H
30H
40H
45H
00H
82H
08H
00H
00H
0CH
08H
70H
38H
01H
02H
00H
03H
30H
3DH
45H
50H
3DH
50H
128 bytes
256 bytes
DDR2 SDRAM
14
10
2
64
0
SSTL 1.8V
2.5ns*
3.0ns*
0.4ns*
1
1
1
0.45ns*
None
7.8µs
×
8
None
0
4,8
8
4, 5, 6
3, 4, 5
1
SDRAM device attributes:
0
Burst length supported
SDRAM device attributes: Number of
0
banks on SDRAM device
SDRAM device attributes: /CAS
latency
0
-8G
-6E
0
0
0
0
0
0
0
0
0
0
0
19
20
21
22
23
DIMM Mechanical Characteristics
DIMM type information
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
CL = X
−
1
-8G (CL = 5)
-6E (CL = 4)
Maximum data access time (tAC)
from clock at CL = X
−
1
-8G (CL = 5)
-6E (CL = 4)
Minimum clock cycle time at
CL = X
−
2
-8G (CL = 4)
-6E (CL = 3)
4.00mm max.
Unbuffered
Normal
Weak Driver
50Ω ODT Support
3.0ns*
1
3.75ns*
0.45ns*
0.5ns*
1
1
24
1
25
3.75ns*
5.0ns*
1
1
Preliminary Data Sheet E1401E10 (Ver. 1.0)
5
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