5962-9957201NTB datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> 5962-9957201NTB

5962-9957201NTB: DescriptionQPro Virtex 2.5V QML High-Reliability FPGAs; CategoryProgrammable logic devices Programmable logic; File Size230KB，31 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

Download Datasheet Parametric View All

5962-9957201NTB Overview

QPro Virtex 2.5V QML High-Reliability FPGAs

5962-9957201NTB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	QFP, QFP240,1.3SQ,20
Contacts	240
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
Combined latency of CLB-Max	0.8 ns
JESD-30 code	S-PQFP-G240
JESD-609 code	e0
length	32 mm
Configurable number of logic blocks	1536
Equivalent number of gates	322970
Number of entries	166
Number of logical units	6912
Output times	166
Number of terminals	240
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	322970 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP240,1.3SQ,20
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.2/3.6,2.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Qualified
Filter level	MIL-PRF-38535
Maximum seat height	4.1 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	32 mm
Base Number Matches	1

Preview

Download Datasheet

View All

QPro Virtex 2.5V QML

High-Reliability FPGAs

DS002 (v1.5) December 5, 2001

Preliminary Product Specification

•

0.22

µm

5-layer metal process

100% factory tested

Available to Standard Microcircuit Drawings

5962-99572 for XQV300

5962-99573 for XQV600

5962-99574 for XQV1000

Contact Defense Supply Center Columbus (DSCC)

for more information at

http://www.dscc.dla.mil

Features

•

Certified to MIL-PRF-38535 (Qualified Manufacturer

Listing)

Guaranteed over the full military temperature range

(–55°C to +125°C)

Ceramic and Plastic Packages

Fast, high-density Field-Programmable Gate Arrays

•

Densities from 100K to 1M system gates

System performance up to 200 MHz

Hot-swappable for Compact PCI

16 high-performance interface standards

Connects directly to ZBTRAM devices

Four dedicated delay-locked loops (DLLs) for

advanced clock control

Four primary low-skew global clock distribution

nets, plus 24 secondary global nets

LUTs configurable as 16-bit RAM, 32-bit RAM,

16-bit dual-ported RAM, or 16-bit Shift Register

Configurable synchronous dual-ported 4K-bit

RAMs

Fast interfaces to external high-performance RAMs

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

Internal 3-state bussing

IEEE 1149.1 boundary-scan logic

Die-temperature sensing device

Description

The QPro™ Virtex™ FPGA family delivers high-perfor-

mance, high-capacity programmable logic solutions. Dra-

matic increases in silicon efficiency result from optimizing

the new architecture for place-and-route efficiency and

exploiting an aggressive 5-layer-metal 0.22

µm

CMOS pro-

cess. These advances make QPro Virtex FPGAs powerful

and flexible alternatives to mask-programmed gate arrays.

The Virtex family comprises the four members shown in

Table 1.

Building on experience gained from previous generations of

FPGAs, the Virtex family represents a revolutionary step

forward in programmable logic design. Combining a wide

variety of programmable system features, a rich hierarchy of

fast, flexible interconnect resources, and advanced process

technology, the QPro Virtex family delivers a high-speed

and high-capacity programmable logic solution that

enhances design flexibility while reducing time-to-market.

Refer to the

“Virtex™ 2.5V Field Programmable Gate

Arrays”

commercial data sheet for more information on

device architecture and timing specifications.

Multi-standard SelectI/O™ interfaces

Built-in clock-management circuitry

Hierarchical memory system

•

Flexible architecture that balances speed and density

•

Supported by FPGA Foundation™ and Alliance

Development Systems

Complete support for Unified Libraries, Relationally

Placed Macros, and Design Manager

Wide selection of PC and workstation platforms

Unlimited reprogrammability

Four programming modes

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

•

SRAM-based in-system configuration

DS002 (v1.5) December 5, 2001

Preliminary Product Specification

www.xilinx.com

1-800-255-7778

Recommended Resources

Projector lamp AC automatic voltage regulation circuit circuit diagram

High voltage electric fence circuit

Simple light control switch circuit

Self-extinguishing super regenerative receiving circuit

Delay circuit using operational amplifier

Application of Dual-Gate SiC FETs in Circuit Protection: According to reports, Qorvo is a company that focuses on the RF field and has invested in communication technologies including 5G, WiFi and UWB. In addition, Qorvo also has layouts in touch and power ...; btty038 Energy Infrastructure?

[Boliu BL606P audio and video development board] ADC test-virtual oscilloscope Demo: PrefaceIn the previous article, we tested IO, and this article continues the ADC interface test. We can collect ADC values and print them from the serial port, and then the PC receives the printed val...; qinyunti XuanTie RISC-V Activity Zone

[Sipeed BL808 all-round board] - Image processing test routine - tinymaix_mnist_demo: # 2.2 Image processing test routine - tinymaix_mnist_demo Tinymaix is an open source super lightweight neural network inference library for microcontrollers developed by Sipeed. This library does not ...; IC爬虫 Domestic Chip Exchange

[Boliu BL606P audio and video development board] PWM test-breathing light effect realization: Preface In this article, we continue the interface test, test the PWM output, test its frequency and duty cycle settings, and use PWM to control the LED to achieve the effect of a breathing light. pro...; qinyunti XuanTie RISC-V Activity Zone

[Boliu BL606P audio and video development board] coremark benchmark performance test: Preface According to the evaluation plan, we will conduct performance testing in this article. There are many types of CPU benchmark performance tests, the most common one is coremark, and we will use...; qinyunti XuanTie RISC-V Activity Zone

ESP32-C6 has a development board, where is C5?: I have been paying attention to the 2.4GHz and 5GHz dual-band WiFi of ESP32-C5. Now that ESP32-C6 has a development board, why is ESP32-C5 not yet in mass production? Does anyone have any gossip?...; buildele RF/Wirelessly

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components