EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

SVX90KL

Description
SmartOnline SVX Series 90kVA Modular, Scalable 3-Phase, On-line Double-Conversion 400/230V 50/60Hz UPS System
File Size181KB,6 Pages
ManufacturerTripp Lite
Websitehttps://www.tripplite.com/
Download Datasheet View All

SVX90KL Overview

SmartOnline SVX Series 90kVA Modular, Scalable 3-Phase, On-line Double-Conversion 400/230V 50/60Hz UPS System

I'm looking for a classmate to make a digital display screen for calling numbers
[i=s] This post was last edited by jameswangsynnex on 2015-3-3 19:51 [/i] Use the keys to input the value to the small screen and display it. At the same time, the small screen is connected to the lar...
瀚鑫 Mobile and portable
Mobile phone embedded software programmer--how to learn?
Hello everyone, I am a college student who just graduated. I learned C/C++ and now work in a software company. Our company is engaged in "mobile phone embedded software program development". The main ...
天雪 Embedded System
Comparison between LLC resonant converter and asymmetric half-bridge converter
Abstract: Two different types of soft switching topologies, LLC resonant converter and asymmetric half-bridge converter, are introduced . Their working principles are analyzed, and their control metho...
zbz0529 Power technology
GigaDevice GD32307E-START Review Summary
Event details: https://bbs.eeworld.com.cn/elecplay/content/139Evaluation report summary: @jiajiabin【GD32307E-START】Light up an LED@Shen Xiaolin【GD32307E-START】-Unboxing and post-test planning 【GD32307...
okhxyyo GD32 MCU
Ask for help on "2ASK communication system design"
Hello everyone~~ I need help~~~ I need to use EDA to design a modulation system. The general idea is as follows: use AND gates to make a multiplier, use counters to make a frequency divider to divide ...
大漠风云 FPGA/CPLD
I would like to ask the master, a statement occupies more than 90,000 logic units in FPGA
The statements are: input wire[11:0] addr, // connected to dsp_ea[14:3] output reg[16:0] q, reg[7:0] headers[0:256*8-1], //'define TEST 'ifdef TEST .... 'else always@(posedge clk)begin if(rden)begin q...
lakas FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 137  1265  317  516  1734  3  26  7  11  35 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号