32K
X24320
400KHz 2-Wire Serial E
2
PROM with Block Lock
™
4Kx 8 Bit
FEATURES
• Save Critical Data with Programmable Block
Lock Protection
—Block lock (0, 1/4, 1/2, or all of E
2
PROM array)
—Software write protection
—Programmable hardware write protect
• In Circuit Programmable ROM Mode
• 400KHz 2-Wire Serial Interface
—Schmitt trigger input noise suppression
—Output slope control for ground bounce noise
elimination
• Longer Battery Life With Lower Power
—Active read current less than 1mA
—Active write current less than 3mA
—Standby current less than 1µA
• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power
Supply Versions
• 32 Word Page Write Mode
—Minimizes total write time per word
• Internally Organized 4K x 8
• Bidirectional Data Transfer Protocol
• Self-Timed Write Cycle
—Typical write cycle time of 5ms
• High Reliability
—Endurance: 1 million cycles
—Data retention: 100 years
• 8-Lead SOIC
• 14-Lead TSSOP
—8-Lead PDIP
BLOCK DIAGRAM
Serial E
2
PROM Data
and Address (SDA)
SCL
Command
Decode
and
Control
Logic
DESCRIPTION
The X24320 is a CMOS Serial E
2
PROM, internally
organized 4K x 8. The device features a serial interface
and software protocol allowing operation on a simple
two wire bus. The bus operates at 400 KHz all the way
down to 1.8V.
Three device select inputs (S
0
–S
2
) allow up to eight
devices to share a common two wire bus.
A Write Protect Register at the highest address location,
FFFFh, provides three write protection features: Software
Write Protect, Block Lock Protect, and Programmable
Hardware Write Protect. The Software Write Protect
feature prevents any nonvolatile writes to the device
until the WEL bit in the Write Protect Register is set.
The Block Lock Protection feature gives the user four
array block protect options, set by programming two bits
in the Write Protect Register. The Programmable Hard-
ware Write Protect feature allows the user to install the
device with WP tied to V
CC
, write to and Block Lock the
desired portions of the memory array in circuit, and then
enable the In Circuit Programmable ROM Mode by pro-
gramming the WPEN bit HIGH in the Write Protect Reg-
ister. After this, the Block Locked portions of the array,
including the Write Protect Register itself, are perma-
nently protected from being erased.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
Data Register
Y Decode Logic
Serial E
2
PROM
Array
4K x 8
1K x 8
Block Lock and
Write Protect
Control Logic
1K x 8
Write
Protect
Register
Page
Decode
Logic
S
2
S
1
S
0
WP
Device
Select
Logic
2K x 8
Write Voltage
Control
©
Xicor, Inc. 2000 Patents Pending
7035-1.2 10/27/00 EP
Characteristics subject to change without notice.
1 of 18
X24320
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-up
resistor selection graph at the end of this data sheet.
Device Select (S
0
, S
1
, S
2
)
The device select inputs (S
0
, S
1
, S
2
) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to V
SS
or V
CC
as appropri-
ate. If actively driven, they must be driven with CMOS
levels (driven to V
CC
or V
SS
).
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write Pro-
tection is disabled. When this input is held HIGH, and
the WPEN bit in the Write Protect Register is set HIGH,
the Write Protect Register is protected, preventing
changes to the Block Lock Protection and WPEN bits.
PIN NAMES
Symbol
S
0
, S
1
, S
2
SDA
SCL
WP
V
SS
V
CC
NC
PIN CONFIGURATION
8-Lead DIP/SOIC
S
0
S
1
S
2
V
SS
1
2
3
4
X24320
8
7
6
5
V
CC
WP
SCL
SDA
14-Lead TSSOP
S
0
S
1
NC
NC
NC
S
2
V
SS
1
2
3
4
5
6
7
X24320
14
13
12
11
10
9
8
V
CC
WP
NC
NC
NC
SCL
SDA
DEVICE OPERATION
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Description
Device Select Inputs
Serial Data
Serial Clock
Write Protect
Ground
Supply Voltage
No Connect
Characteristics subject to change without notice.
2 of 18
X24320
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
START Bit
STOP Bit
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL From
Master
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
1
8
9
Data Output
From Transmitter
Data Output
From Receiver
START
Acknowledge
Characteristics subject to change without notice.
3 of 18
X24320
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S
0
, S
1
, and S
2
. This allows up to 8
devices to share a single bus. These bits are compared
to the S
0
, S
1
, and S
2
device select input pins. The last
bit of the Slave Address Byte defines the operation to
be performed. When the R/W bit is a one, then a read
operation is selected. When it is zero then a write oper-
ation is selected. Refer to figure 4. After loading the
Slave Address Byte from the SDA bus, the device com-
pares the device type bits with the value “1010” and the
device select bits with the status of the device select
input pins. If the compare is not successful, no
acknowledge is output during the ninth clock cycle and
the device returns to the standby mode.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
The internal organization of the E array is 128 pages
by 32 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 5 of the Word Address Byte 0. The byte
address is contained in bits 4 through 0 of the Word
Address Byte 0. See Figure 4.
2
Figure 4. Device Addressing
Device Type
Identifier
Device
Select
1
0
1
0
S
2
S
1
S
0
R/W
SLAVE ADDRESS BYTE
High Order Word Address
0
0
0
0
A11 A10
A9
A8
X24320 WORD ADDRESS BYTE 1
Low Order Address
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS BYTE 0
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
Characteristics subject to change without notice.
4 of 18
X24320
WRITE OPERATIONS
Byte Write
For a write operation, the device requires the Slave
Address Byte, the Word Address Byte 1, and the Word
Address Byte 0, which gives the master access to any
one of the words in the array. Upon receipt of the Word
Address Byte 0, the device responds with an acknowl-
edge, and waits for the first eight bits of data. After
receiving the 8 bits of the data byte, the device again
responds with an acknowledge. The master then termi-
nates the transfer by generating a stop condition, at
which time the device begins the internal write cycle to
the nonvolatile memory. While the internal write cycle
is in progress the device inputs are disabled and the
device will not respond to any requests from the
master. The SDA pin is at high impedance. See
Figure 5.
Page Write
The device is capable of a thirty-two byte page write
operation. It is initiated in the same manner as the byte
write operation; but instead of terminating the write
operation after the first data word is transferred, the
master can transmit up to thirty-one more words. The
device will respond with an acknowledge after the
receipt of each word, and then the byte address is
internally incremented by one. The page address
remains constant. When the counter reaches the end
of the page, it “rolls over” and goes back to the first
byte of the current page. This means that the master
can write 32 words to the page beginning at any byte. If
the master begins writing at byte 16, and loads 32
words, then the first 16 words are written to bytes 16
through 31, and the last 16 words are written to bytes 0
through 15. Afterwards, the address counter would
point to byte 16. If the master writes more than 32
words, then the previously loaded data is overwritten
by the new data, one byte at a time.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write opera-
tion, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address,
acknowledge, and data transfer sequence.
Figure 5. Byte Write Sequence
S
T
A
R
T
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Master
SDA Bus
Signals From
The Slave
Slave
Address
0
Word Address
Byte 1
Word Address
Byte 0
Data
S1 0 1 0
Figure 6. Page Write Sequence
(0
≤
n
≤
31)
Signals From
The Master
SDA Bus
Signals From
The Slave
S
T
A
R
T
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
Data
(0)
Data
(n)
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S 1010
0
Characteristics subject to change without notice.
5 of 18
MCU
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