ENHANCED SMMIT FAMILY
Product Handbook
TM
Aeroflex Colorado Springs, Inc.
4350 Centennial Blvd.
Colorado Springs, CO 80907
October 12, 2015
I
Table of Contents
1.0 INTRODUCTION
1.1 Remote Terminal Features
1.1.1 Indexing
1.1.2 Buffer Ping-Pong
1.1.3 Circular Buffers
1.1.4 Internal Illegalization
1.1.5 Broadcast
1.1.6 Interrupt History
1.1.7 Message Information
1.2 Bus Controller Features
1.2.1 Multiple Message Processing
1.2.2 Message Scheduling
1.2.3 Polling
1.2.4 Automatic Retry
1.3 Monitor Terminal Features
1.3.1 Message Information
1.4 Remote Terminal/Monitor Terminal Features
1.5 Protocol Definition
1.6 SMMIT Transceivers
1.7 SMMIT XTE Memory
2.0 REMOTE TERMINAL ARCHITECTURE
2.1 Register Descriptions
2.1.1 Control Register
2.1.2 Operational Status Register
2.1.3 Current Command Register
2.1.4 Interrupt Mask Register
2.1.5 Pending Interrupt Register
2.1.6 Interrupt Log List Pointer Register
2.1.7 Bit Word Register
2.1.8 Time-Tag Register
2.1.9 Remote Terminal Descriptor Pointer Register
2.1.10 1553 Status Word Bits Register
2.1.11 Illegalization Registers
2.2 Descriptor Block
2.2.1 Receive Control Word
2.2.2 Transmit Control Word
2.2.3 Mode Code Receive Control Word
2.2.4 Mode Code Transmit Control Word
2.2.5 Data Pointer A and B
2.2.6 Broadcast Data Pointer
2.3 Data Structures
2.3.1 Subaddress Receive Data
2.3.2 Subaddress Transmit Data
II
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
6
6
6
8
9
10
10
12
12
13
13
14
16
18
21
22
23
24
25
25
25
28
28
2.3.2.1 Transmit Information (Info) Word
2.3.3 Mode Code Data
2.3.3.1 Mode Code Receive Information (Info) Word
2.3.3.2 Mode Code Transmit Information (Info) Word
2.4 Mode Code and Subaddress
2.5 Encoder and Decoder
2.6 RT-RT Transfer Compare
2.7 Terminal Address
2.8 Reset
2.9 MIL-STD-1553A Operation
3.0 BUS CONTROLLER ARCHITECTURE
3.1 Register Descriptions
3.1.1 Control Register
3.1.2 Operational Status Register
3.1.3 Current Command Register
3.1.4 Interrupt Mask Register
3.1.5 Pending Interrupt Register
3.1.6 Interrupt Log List Pointer Register
3.1.7 BIT Word Register
3.1.8 Minor Frame Timer Register
3.1.9 Command Block Pointer Register
3.1.10 BC Command Block Initialization Control Register
3.2 SBC Architecture
3.2.1 Control Word
3.2.1.1 Opcode Definition
3.2.1.2 Condition Codes
3.2.2 Command Words
3.2.3 Data Pointer
3.2.4 Status Words
3.2.5 Branch Address
3.2.6 Timer Value
3.3 Command Block Chaining
3.4 Memory Architecture
3.5 Message Processing
3.6 MIL-STD-1553A Operation
4.0 MONITOR TERMINAL ARCHITECTURE
4.1 Register Descriptions
4.1.1 Control Register
4.1.2 Operational Status Register
4.1.3 Current Command Register
4.1.4 Interrupt Mask Register
4.1.5 Pending Interrupt Register
4.1.6 Interrupt Log List Pointer Register
4.1.7 BIT Word Register
4.1.8 Time-Tag Register
4.1.9 Initial Monitor Block Pointer Register
III
29
29
30
30
31
33
33
33
33
34
35
35
36
37
38
38
39
40
40
40
41
41
42
43
44
45
45
45
46
46
46
46
48
49
50
51
51
52
53
54
54
55
55
56
56
56
4.1.10 Initial Monitor Data Pointer Register
4.1.11 Monitor Block Counter Register
4.1.12 Monitor Filter Register
4.1.13 Monitor Filter Register
4.2 SMT Architecture
4.2.1 Message Information Word
4.2.1.1 Message Information Bits
4.2.2 Command Words
4.2.3 Data Pointer
4.2.4 Status Words
4.2.5 Time-Tag
4.2.6 Unused
4.3 Monitor Block Chaining
4.4 Memory Architecture
4.5 Message Processing
4.5.1 Error Condition Message Processing
4.6 Remote Terminal/Monitor Terminal Operation
4.7 MIL-STD-1553A Operation
5.0 ENHANCED SMMIT FAMILY OPERATION
5.1 Message Time-out
5.2 DMA Time-out
5.3 Circular Buffers
5.3.1 Mode Number 0
5.3.2 Mode Number 1
5.3.3 Mode Number 2
5.4 Ping-Pong Handshake
5.5 Circular Buffer #1
5.6 Circular Buffer #2
5.7 Ping-Pong Enable/Disable Handshake
6.0 INTERRUPT ARCHITECTURE
6.1 SMMIT E & SMMIT LXE/DXE
6.1.1 Interrupt Identification Word (IIW)
6.1.2 Interrupt Address Word (IAW)
6.1.3 Interrupt Log List Address
6.2 SMMIT XTE
6.2.1 Interrupt Identification Word (IIW)
6.2.2 Interrupt Address Word (IAW)
6.2.3 Interrupt Log List Address
7.0 AUTO-INITIALIZATION
7.1 SMMIT E & SMMIT LXE/DXE
7.1.1 SRT Auto-Initialization
7.1.2 SMT Auto-Initialization
7.1.3 SBC Auto-Initialization
7.1.4 Auto-Initialization Hardware
7.2 SMMIT XTE
IV
57
57
57
57
58
58
59
59
59
59
59
59
60
60
61
61
61
62
63
63
63
63
63
63
64
64
64
66
68
71
71
71
71
71
74
74
74
74
76
76
76
76
76
76
78
7.2.1
7.2.2
7.2.3
7.2.4
SRT Auto-Initialization
SMT Auto-Initialization
SBC Auto-Initialization
Auto-Initialization Hardware
78
78
78
78
81
82
82
82
83
84
84
84
87
87
87
87
87
94
94
94
94
97
98
98
99
99
100
100
101
101
103
103
104
105
106
106
107
107
108
108
109
110
8.0 TESTABILITY
9.0 SYSTEM CONFIGURATION
9.1 SMMIT E & SMMIT LXE/DXE
9.1.1 Transmitter/Receiver Interface
9.1.2 Register Transfers
9.1.3 DMA Configuration
9.1.4 DMA Transfers
9.1.5 Buffer Mode Operation
9.2 SMMIT XTE
9.2.1 Internal Registers
9.2.2 Memory Map
9.2.3 Buffer Mode Operation
9.2.4 Hardware Interface
10.0 SERIAL DATA BUS INTERFACE
10.1 Transmitter
10.2 Receiver
10.3 Recommended Thermal Protection
11.0 SMMIT PIN IDENTIFICATION AND DESCRIPTION
11.1 SMMIT Functional Pin Description
11.1.1 Data Bus
11.1.2 Address Bus
11.1.3 Remote Terminal Address Inputs
11.1.4 JTAG Testability Pins
11.1.5 Biphase Inputs
11.1.6 Biphase Outputs
11.1.7 DMA Signals
11.1.8 Control Signals
11.1.9 Status Signals
11.1.10 Power/Ground
12.0 SMMIT LX/DX PIN IDENTIFICATION AND DESCRIPTION
12.1 SMMIT Functional Pin Description
12.1.1 Data Bus
12.1.2 Address Bus
12.1.3 Remote Terminal Address Inputs
12.1.4 JTAG Testability Pins
12.1.5 Biphase Inputs/Outputs
12.1.6 DMA Signals
12.1.7 Control Signals
V
京公网安备 11010802033920号
EEWORLD
