Section IV. I/O Standards
This section provides information on Cyclone
™
II single-ended, voltage
referenced, and differential I/O standards.
This section includes the following chapters:
■
■
Chapter 10, Selectable I/O Standards in Cyclone II Devices
Chapter 11, High-Speed Differential Interfaces in Cyclone II Devices
Revision History
The table below shows the revision history for
Chapters 10
and
11.
Chapter(s)
10
Date / Version
Changes Made
November 2004, Updated
Table 10–7.
v1.1
June 2004, v1.0
Added document to the Cyclone II Device
Handbook.
●
●
11
November 2004,
v1.1
June 2004, v1.0
Updated
Table 11–1.
Updated
Figures 11–4, 11–5, 11–7,
and
11–8.
Added document to the Cyclone II Device
Handbook.
Altera Corporation
Section IV–1
Preliminary
I/O Standards
Cyclone II Device Handbook, Volume 1
Section IV–2
Preliminary
Altera Corporation
Chapter 10. Selectable I/O
Standards in Cyclone II
Devices
CII51010-1.1
Introduction
The proliferation of I/O standards and the need for improved I/O
performance have made it critical that low-cost devices have flexible I/O
capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and
LVDS compatibility allow Cyclone™ II devices to connect to other
devices on the same printed circuit board (PCB) that may require different
operating and I/O voltages. With these aspects of implementation easily
manipulated using the Altera
®
Quartus
®
II software, the Cyclone II
device family enables system designers to use low cost FPGAs while
keeping pace with increasing design complexity.
This chapter is a guide to understanding the input and output capabilities
of the Cyclone II devices, including:
■
■
■
■
■
Supported I/O standards
Cyclone II I/O banks
Programmable current drive strength
I/O termination
Pad placement and DC guidelines
f
For information on hot socketing, see the
Hot Socketing, ESD & Power-On
Reset
chapter in Volume 1 of the
Cyclone II Device Handbook.
Cyclone II devices support the I/O standards shown in
Table 10–1.
Supported I/O
Standards
f
See the
DC Characteristics & Timing Specifications
chapter in Volume 1 of
the
Cyclone II Device Handbook,
for more details on the I/O standards
discussed in this section, including target data rates and voltage values
for each I/O standard.
Altera Corporation
November 2004
10–1
Preliminary
Supported I/O Standards
f
See the
External Memory Interfaces in Cyclone II Devices
chapter in
Volume 1 of the
Cyclone II Device Handbook
for information on the I/O
standards supported for external memory applications.
Table 10–1. Cyclone II Supported I/O Standards & Constraints (Part 1 of 2)
V
CCIO
Level
I/O Standard
Type
Input Output
3.3-V LVTTL and LVCMOS
2.5-V LVTTL and LVCMOS
1.8-V LVTTL and LVCMOS
1.5-V LVCMOS
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
HSTL-18 class I
HSTL-18 class II
HSTL-15 class I
HSTL-15 class II
PCI and PCI-X
(2)
Single ended
Single ended
Single ended
Single ended
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Single ended
3.3 V/
2.5 V
3.3 V/
2.5 V
1.8 V/
1.5 V
1.8 V/
1.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
3.3 V
(4)
2.5 V
(4)
1.8 V
3.3 V
2.5 V
1.8 V
1.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
3.3 V
2.5 V
(4)
1.8 V
(4)
Top & Bottom
I/O Pins
Side I/O Pins
User I/O
Pins
v
v
v
v
v
v
v
(1)
CLK, User I/O CLK,
PLL_OUT
DQS
Pins
DQS
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
(1)
v
v
v
v
v
v
v
(1)
v
(1)
v
(1)
v
(1)
v
(1)
v
(1)
v
(1)
v
v
(5)
v
v
v
Differential SSTL-2 class I or Pseudo
class II
differential
(3)
v
(5)
Differential SSTL-18 class I
or class II
Pseudo
differential
(3)
v
(6)
v
(5)
v
(5)
10–2
Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation
November 2004
Selectable I/O Standards in Cyclone II Devices
Table 10–1. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2)
V
CCIO
Level
I/O Standard
Type
Input Output
Differential HSTL-15 class I
or class II
Pseudo
differential
(3)
(4)
1.5 V
(4)
1.8 V
2.5 V
(4)
3.3 V/
2.5 V/
1.8 V/
1.5 V
1.5 V
(4)
1.8 V
(4)
2.5 V
2.5 V
(4)
Top & Bottom
I/O Pins
Side I/O Pins
User I/O
Pins
CLK, User I/O CLK,
PLL_OUT
DQS
Pins
DQS
v
(6)
v
(5)
v
(5)
Differential HSTL-18 class I
or class II
Pseudo
differential
(3)
v
(6)
v
(5)
v
(5)
LVDS
RSDS and mini-LVDS
(7)
LVPECL
(8)
Differential
Differential
Differential
v
v
v
v
v
v
v
v
v
v
Notes to
Table 10–1:
(1)
(2)
(3)
These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.
PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and
bottom I/O pins.
Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and
SSTL inputs and only decode one of them.
This I/O standard is not supported on these I/O pins.
This I/O standard is only supported on the dedicated clock pins.
PLL_OUT
does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.
mini-LVDS and RSDS are only supported on output pins.
LVPECL is only supported on clock inputs.
(4)
(5)
(6)
(7)
(8)
3.3-V LVTTL (EIA/JEDEC Standard JESD8-B)
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVTTL standard defines the DC
interface parameters for digital circuits operating from a 3.0-/3.3-V
power supply and driving or being driven by LVTTL-compatible devices.
The LVTTL input standard specifies a wider input voltage range of
– 0.3 V
≤
V
I
≤
3.9 V. Altera recommends an input voltage range of
– 0.5 V
≤
V
I
≤
4.1 V.
Altera Corporation
November 2004
Preliminary
10–3
Cyclone II Device Handbook, Volume 1
京公网安备 11010802033920号
EEWORLD
