Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
•
Balanced propagation delays
•
All inputs have Schmitt-trigger actions
•
Inputs accepts voltages higher than V
CC
•
Common 3-state output enable input
•
Functionally identical to the ‘533’, ‘563’ and ‘573’
•
For AHC only: operates with CMOS input levels
•
For AHCT only: operates with TTL input levels
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
DESCRIPTION
The 74AHC/AHCT373 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
74AHC373; 74AHCT373
The 74AHC/AHCT373 are octal D-type transparent
latches featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. A Latch
Enable (LE) input and an Output Enable (OE) input are
common to all latches.
The ‘373’ consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the
D
n
inputs enters the latches. In this condition the latches
are transparent, i.e. a latch output will change state each
time its corresponding D-input changes.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The ‘373’ is functionally identical to the ‘533’, ‘563’ and
‘573’, but the ‘533’ and ‘563’ have inverted outputs and the
‘563’ and ‘573’ have a different pin arrangement.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
O
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
PARAMETER
propagation delay
D
n
to Q
n
; LE to Q
n
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
CONDITIONS
AHC
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
4.3
3.0
4.0
10
4.3
3.0
4.0
12
AHCT
ns
pF
pF
pF
UNIT
1999 Nov 23
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FUNCTION TABLE
See note 1.
INPUTS
OPERATING MODES
OE
Enable and read register
(transparent mode)
Latch and read register
Latch register and
disable outputs
Note
1. H = HIGH voltage level;
L
L
L
L
H
H
LE
H
H
L
L
X
X
D
n
L
H
I
h
X
X
74AHC373; 74AHCT373
INTERNAL
LATCHES
L
H
L
H
X
X
OUTPUTS
Q
0
to Q
7
L
H
L
H
Z
Z
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC373D
74AHC373PW
74AHCT373D
74AHCT373PW
PINNING
PIN
1
2, 5, 6, 9, 12, 15, 16
and 19
3, 4, 7, 8, 13, 14, 17
and 18
10
11
20
OE
Q
0
to Q
7
D
0
to D
7
GND
LE
V
CC
SYMBOL
latch outputs
data inputs
ground (0 V)
latch enable input (active HIGH)
DC supply voltage
DESCRIPTION
output enable input (active LOW)
PACKAGES
NORTH AMERICA
PINS
74AHC373D
74AHC373PW DH
74AHCT373D
7AHCT373PW DH
20
20
20
20
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT163-1
SOT360-1
SOT163-1
SOT360-1
1999 Nov 23
3
NXP MCU
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