three-state drivers. This device has an automatic power-down
feature (CE
1
or CE
2
), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
1
and WE in-
puts are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address
pins (A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Functional Description
[1]
The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
INPUT BUFFER
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
CE
1
CE
2
WE
OE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
256 x 32 x 8
ARRAY
COLUMN DECODER
POWER
DOWN
SENSE AMPS
I/O
7
A
10
A
11
Selection Guide
[2]
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
7C185-15
15
130
40/15
7C185-20
20
110
20/15
7C185-25
25
100
20/15
7C185-35
35
100
20/15
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. For military specifications, see the CY7C185A data sheet.
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *A
•
A
12
A
0
A
9
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
CY7C185
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[3]
............................................ –0.5V to +7.0V
DC Input Voltage
[3]
......................................... –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C185-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[4]
V
CC
Operating
Supply Current
Automatic
Power-Down Current
Automatic
Power-Down Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA
Max. V
CC
, CE
1
≥
V
IH
or CE
2
≤
V
IL
Min. Duty Cycle = 100%
Max. V
CC
, CE
1
≥
V
CC
– 0.3V,
or CE
2
≤
0.3V
V
IN
≥
V
CC
– 0.3V or V
IN
≤
0.3V
40
15
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+5
+5
–300
130
20
15
2.2
–0.5
–5
–5
Max.
7C185-20
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+5
+5
–300
110
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Notes:
3. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05043 Rev. *A
Page 2 of 11
CY7C185
Electrical Characteristics
Over the Operating Range (continued)
7C185-25
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[4]
V
CC
Operating
Supply Current
Automatic
Power-Down Current
Automatic
Power-Down Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA
Max. V
CC
, CE
1
≥
V
IH
or CE
2
≤
V
IL
Min. Duty Cycle = 100%
Max. V
CC
, CE
1
≥
V
CC
– 0.3V
or CE
2
≤
0.3V
V
IN
≥
V
CC
– 0.3V or V
IN
≤
0.3V
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+5
+5
–300
100
20
15
2.2
–0.5
–5
–5
Max.
7C185-35
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+5
+5
–300
100
20
15
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
7
7
Unit
pF
pF
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIGAND
SCOPE
R1 481
Ω
ALL INPUT PULSES
3.0V
R2
255Ω
GND
10%
90%
90%
10%
≤
5 ns
R2
255Ω
≤
5 ns
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Document #: 38-05043 Rev. *A
Page 3 of 11
CY7C185
Switching Characteristics
Over the Operating Range
[6]
7C185-15
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
Write Cycle
[9]
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW to Write End
CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[7]
WE HIGH to Low Z
3
15
12
12
12
0
0
12
8
0
7
5
20
15
15
15
0
0
15
10
0
7
5
25
20
20
20
0
0
15
10
0
7
5
35
20
20
25
0
0
20
12
0
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid
CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7]
CE
1
LOW to Low Z
[8]
CE
2
HIGH to Low Z
CE
1
HIGH to High Z
[7, 8]
CE
2
LOW to High Z
CE
1
LOW to Power-Up
CE
2
to HIGH to Power-Up
CE
1
HIGH to Power-Down
CE
2
LOW to Power-Down
0
15
3
3
7
0
20
3
7
5
3
8
0
20
3
15
15
8
3
8
5
3
10
0
20
15
15
5
20
20
9
3
10
5
3
10
20
20
5
25
25
12
3
10
25
25
5
35
35
15
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C185-20
Min.
Max.
7C185-25
Min.
Max.
7C185-35
Min.
Max.
Unit
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. t
HZOE,
t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE1
and t
LZCE2
for any given device.
9. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *A
Page 4 of 11
CY7C185
Switching Waveforms
Read Cycle No.1
[10,11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Read Cycle No.2
[12,13]
CE
1
t
RC
CE
2
OE
OE
t
ACE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
ICC
50%
ISB
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[11,13]
t
WC
ADDRESS
CE
1
t
AW
CE
2
CE
WE
t
SA
t
SCE2
t
PWE
t
SCEI
t
HA
OE
t
SD
DATA I/O
NOTE 14
t
HZOE
10.
11.
12.
13.
Device is continuously selected. OE, CE
1
= V
IL
. CE
2
= V
IH
.
WE is HIGH for read cycle.
Data I/O is High Z if OE = V
IH
, CE
1
= V
IH
, WE = V
IL
, or CE
2
=V
IL
.
The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH and WE LOW. CE
1
and WE must be LOW and CE
2
must be HIGH
to initiate write. A write can be terminated by CE
1
or WE going HIGH or CE
2
going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
14. During this period, the I/Os are in the output state and input signals should not be applied.
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