CD74HC73E datasheet, PDF - EEWORLD Datasheet

CD74HC73E: DescriptionHigh Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125; Categorylogic logic; File Size727KB，18 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	compli
ECCN code	EAR99
Factory Lead Time	12 weeks
Samacsys Descripti	High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Rese
series	HC
JESD-30 code	R-PDIP-T14
JESD-609 code	e4
length	19.305 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Su	20000000 Hz
MaximumI(ol)	0.006 A
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2/6 V
Maximum supply current (ICC)	0.04 mA
Prop。Delay @ Nom-Su	40 ns
propagation delay (tpd)	240 ns
Certification status	Not Qualified
Schmitt trigger	N
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	7.62 mm
minfmax	23 MHz

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