5962-9167701ZC datasheet, PDF - EEWORLD Datasheet

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5962-9167701ZC: DescriptionFIFO, 8KX9, 80ns, Asynchronous, CMOS, CQCC32, CERAMIC, LCC-32; Categorystorage storage; File Size187KB，25 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

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5962-9167701ZC Overview

FIFO, 8KX9, 80ns, Asynchronous, CMOS, CQCC32, CERAMIC, LCC-32

5962-9167701ZC Parametric

Parameter Name	Attribute value
Maker	TEMIC
package instruction	CERAMIC, LCC-32
Reach Compliance Code	unknown
Maximum access time	80 ns
Other features	RETRANSMIT
period time	100 ns
JESD-30 code	R-CQCC-N32
memory density	73728 bit
memory width	9
Number of functions	1
Number of terminals	32
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	8KX9
Exportable	NO
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal location	QUAD
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Boilerplate update, part of 5 year review.

ksr

DATE (YR-MO-DA)

07-01-29

APPROVED

Joseph Rodenbeck

THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Jeffery D. Bowling

CHECKED BY

Raymond Monnin

APPROVED BY

Michael A. Frye

DRAWING APPROVAL DATE

92-09-25

REVISION LEVEL

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

MICROCIRCUIT, MEMORY,

DIGITAL, CMOS, 8K X 9 DUAL

PORT FIFO, MONOLITHIC

SILICON

SIZE

SHEET

1 OF

5962-E015-07

CAGE CODE

67268

5962-91677

AMSC N/A

DSCC FORM 2233

APR 97

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 2.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and

herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for

device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 105 (see MIL-PRF-38535, appendix A).

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-91677

SHEET

4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in

accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

4.2.1 Additional criteria for device class M.

Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)

electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.

The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,

and power dissipation, as applicable, in accordance with the intent specified in method 1015.

(1)

Dynamic burn-in (method 1015 of MIL-STD-883, test condition D for circuit, see 4.2.1b herein).

Interim and final electrical parameters shall be as specified in table IIA herein.

4.2.2 Additional criteria for device classes Q and V.

The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the

device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under

document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with

MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

method 1015 of MIL-STD-883.

Interim and final electrical test parameters shall be as specified in table IIA herein.

Additional screening for device class V beyond the requirements of device class Q shall be as specified in

MIL-PRF-38535, appendix B.

4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in

accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups

A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-91677

SHEET

5962-9167701ZC Related Products

	5962-9167701ZC	5962-9167702XX	5962-9167701XA	5962-9167701XX	5962-9167702ZX	5962-9167701ZX	5962-9167702XA
Description	FIFO, 8KX9, 80ns, Asynchronous, CMOS, CQCC32, CERAMIC, LCC-32	FIFO, 8KX9, 50ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28	FIFO, 8KX9, 80ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28	FIFO, 8KX9, 80ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28	FIFO, 8KX9, 50ns, Asynchronous, CMOS, CQCC32, CERAMIC, LCC-32	FIFO, 8KX9, 80ns, Asynchronous, CMOS, CQCC32, CERAMIC, LCC-32	FIFO, 8KX9, 50ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28
package instruction	CERAMIC, LCC-32	CERAMIC, DIP-28	CERAMIC, DIP-28	CERAMIC, DIP-28	CERAMIC, LCC-32	CERAMIC, LCC-32	CERAMIC, DIP-28
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Maximum access time	80 ns	50 ns	80 ns	80 ns	50 ns	80 ns	50 ns
Other features	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT
period time	100 ns	65 ns	100 ns	100 ns	65 ns	100 ns	65 ns
JESD-30 code	R-CQCC-N32	R-GDIP-T28	R-GDIP-T28	R-GDIP-T28	R-CQCC-N32	R-CQCC-N32	R-GDIP-T28
memory density	73728 bit	73728 bit	73728 bit	73728 bit	73728 bit	73728 bit	73728 bit
memory width	9	9	9	9	9	9	9
Number of functions	1	1	1	1	1	1	1
Number of terminals	32	28	28	28	32	32	28
word count	8192 words	8192 words	8192 words	8192 words	8192 words	8192 words	8192 words
character code	8000	8000	8000	8000	8000	8000	8000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	8KX9	8KX9	8KX9	8KX9	8KX9	8KX9	8KX9
Exportable	NO	NO	NO	NO	NO	NO	NO
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED
encapsulated code	QCCN	DIP	DIP	DIP	QCCN	QCCN	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE	IN-LINE	IN-LINE	CHIP CARRIER	CHIP CARRIER	IN-LINE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	NO	NO	YES	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	NO LEAD	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	NO LEAD	NO LEAD	THROUGH-HOLE
Terminal location	QUAD	DUAL	DUAL	DUAL	QUAD	QUAD	DUAL
Base Number Matches	1	1	1	1	1	1	1
Maker	TEMIC	-	TEMIC	TEMIC	TEMIC	TEMIC	TEMIC

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